From: Luke Kenneth Casson Leighton Date: Thu, 26 Mar 2020 15:15:06 +0000 (+0000) Subject: Re: [libre-riscv-dev] cache SRAM organisation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8574cf9076fbbd6613d23557427817d929e99ebd;p=libre-riscv-dev.git Re: [libre-riscv-dev] cache SRAM organisation --- diff --git a/be/d05f898b65bc1e1030656763b92e7e525110fb b/be/d05f898b65bc1e1030656763b92e7e525110fb new file mode 100644 index 0000000..50897e8 --- /dev/null +++ b/be/d05f898b65bc1e1030656763b92e7e525110fb @@ -0,0 +1,132 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Thu, 26 Mar 2020 15:15:32 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHUEF-0000Aj-F5; Thu, 26 Mar 2020 15:15:31 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jHUEC-0000AX-El + for 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