From: Kenneth Ryerson <kryerson@vermeer.com>
Date: Mon, 3 Jun 2013 19:52:21 +0000 (+0200)
Subject: csr/sram: fix reads on high addresses when word_bits != 0
X-Git-Tag: 24jan2021_ls180~2099^2~568
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85813b3b586313a63bcb1b84ba22a176c3344b6e;p=litex.git

csr/sram: fix reads on high addresses when word_bits != 0
---

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index fd812e9a..b0ed1966 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -107,10 +107,10 @@ class SRAM(Module):
 				]
 		
 		if self._page is None:
-			self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
+			self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
 		else:
 			pv = self._page.storage
-			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
+			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
 
 	def get_csrs(self):
 		if self._page is None: