From: lkcl Date: Sun, 5 Sep 2021 14:11:20 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~233 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=859492fc6279f22f115eceb128f293a25f6974ac;p=libreriscv.git --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index f8d5cbb95..47414bce7 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -287,6 +287,11 @@ required. useful, because it can be used to truncate VL to the first predicated (non-masked-out) element. +*Programming note: One important point is that SVP64 instructions are 64 bit. +(8 bytes not 4). This needs to be taken into consideration when computing +branch offsets: the offset is relative to the start of the instruction, +which includes the SVP64 Prefix* + Available options to combine: * `BO[0]` to make an unconditional branch would seem irrelevant if @@ -303,11 +308,6 @@ In addition to the above, it is necessary to select whether, in `svstep` mode, the Vector CR Field is to be overwritten or not: in some cases it is useful to know but in others all that is needed is the branch itself. -*Programming note: One important point is that SVP64 instructions are 64 bit. -(8 bytes not 4). This needs to be taken into consideration when computing -branch offsets: the offset is relative to the start of the instruction, -which includes the SVP64 Prefix* - # Pseudocode and examples Pseudocode for Horizontal-First Mode: