From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Jul 2021 15:31:08 +0000 (+0100)
Subject: ffmuls test, had to add to b not a in expected results
X-Git-Tag: xlen-bcd~330
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=859936f2118f87d1b1ddec0f762a1a3b72a23ad9;p=openpower-isa.git

ffmuls test, had to add to b not a in expected results
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 3001050b..181de643 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -185,7 +185,7 @@ class DecoderTestCase(FHDLTestCase):
             fprs[i+6] = fp64toselectable(b)
             fprs[i+10] = fp64toselectable(c)
             mul = a * c
-            t = a + mul
+            t = b + mul
             u = b - mul
             t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
             u = DOUBLE2SINGLE(fp64toselectable(u)) # from double