From: H.J. Lu Date: Sat, 3 Dec 2022 02:43:20 +0000 (-0800) Subject: x86: Allow 16-bit register source for LAR and LSL X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=859aa2c86dc9;p=binutils-gdb.git x86: Allow 16-bit register source for LAR and LSL Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated. --- diff --git a/gas/testsuite/gas/i386/i386-intel.d b/gas/testsuite/gas/i386/i386-intel.d index 28025ca237a..42f86692d60 100644 --- a/gas/testsuite/gas/i386/i386-intel.d +++ b/gas/testsuite/gas/i386/i386-intel.d @@ -62,4 +62,24 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[eax\] [ ]*[a-f0-9]+: 0f b7 00 movzx eax,WORD PTR \[eax\] [ ]*[a-f0-9]+: 0f c3 00 movnti DWORD PTR \[eax\],eax +[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\] +[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\] +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\] +[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\] +[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\] +[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\] +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\] +[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\] #pass diff --git a/gas/testsuite/gas/i386/i386.d b/gas/testsuite/gas/i386/i386.d index 6863bb51618..b5a5565adf6 100644 --- a/gas/testsuite/gas/i386/i386.d +++ b/gas/testsuite/gas/i386/i386.d @@ -61,4 +61,24 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax [ ]*[a-f0-9]+: 0f b7 00 movzwl \(%eax\),%eax [ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%eax\) +[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx +[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx +[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx +[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx +[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx +[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx #pass diff --git a/gas/testsuite/gas/i386/i386.s b/gas/testsuite/gas/i386/i386.s index 97bb1a4e3b4..a42eafb8958 100644 --- a/gas/testsuite/gas/i386/i386.s +++ b/gas/testsuite/gas/i386/i386.s @@ -66,3 +66,27 @@ movzx eax, byte ptr [eax] movzx eax, word ptr [eax] movnti dword ptr [eax], eax + + .att_syntax + lar %dx,%dx + lar %dx,%edx + lar %edx,%edx + lar (%edx),%dx + lar (%edx),%edx + lsl %dx,%dx + lsl %dx,%edx + lsl %edx,%edx + lsl (%edx),%dx + lsl (%edx),%edx + + .intel_syntax noprefix + lar dx,dx + lar edx,dx + lar edx,edx + lar dx,WORD PTR [edx] + lar edx,WORD PTR [edx] + lsl dx,dx + lsl edx,dx + lsl edx,edx + lsl dx,WORD PTR [edx] + lsl edx,WORD PTR [edx] diff --git a/gas/testsuite/gas/i386/intel-intel.d b/gas/testsuite/gas/i386/intel-intel.d index 73fbdf89c1c..609781f3f78 100644 --- a/gas/testsuite/gas/i386/intel-intel.d +++ b/gas/testsuite/gas/i386/intel-intel.d @@ -699,11 +699,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\] [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\] [ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnp dx,WORD PTR \[eax-0x6f6f6f70\] -[ ]*[a-f0-9]+: 0f 02 c0 + lar eax,eax +[ ]*[a-f0-9]+: 0f 02 c0 + lar eax,ax [ ]*[a-f0-9]+: 66 0f 02 c0 + lar ax,ax [ ]*[a-f0-9]+: 0f 02 00 + lar eax,WORD PTR \[eax\] [ ]*[a-f0-9]+: 66 0f 02 00 + lar ax,WORD PTR \[eax\] -[ ]*[a-f0-9]+: 0f 03 c0 + lsl eax,eax +[ ]*[a-f0-9]+: 0f 03 c0 + lsl eax,ax [ ]*[a-f0-9]+: 66 0f 03 c0 + lsl ax,ax [ ]*[a-f0-9]+: 0f 03 00 + lsl eax,WORD PTR \[eax\] [ ]*[a-f0-9]+: 66 0f 03 00 + lsl ax,WORD PTR \[eax\] diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d index 374f8753396..65e79e6ebde 100644 --- a/gas/testsuite/gas/i386/intel.d +++ b/gas/testsuite/gas/i386/intel.d @@ -698,11 +698,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx [ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%dx -[ ]*[a-f0-9]+: 0f 02 c0 lar %eax,%eax +[ ]*[a-f0-9]+: 0f 02 c0 lar %ax,%eax [ ]*[a-f0-9]+: 66 0f 02 c0 lar %ax,%ax [ ]*[a-f0-9]+: 0f 02 00 lar \(%eax\),%eax [ ]*[a-f0-9]+: 66 0f 02 00 lar \(%eax\),%ax -[ ]*[a-f0-9]+: 0f 03 c0 lsl %eax,%eax +[ ]*[a-f0-9]+: 0f 03 c0 lsl %ax,%eax [ ]*[a-f0-9]+: 66 0f 03 c0 lsl %ax,%ax [ ]*[a-f0-9]+: 0f 03 00 lsl \(%eax\),%eax [ ]*[a-f0-9]+: 66 0f 03 00 lsl \(%eax\),%ax diff --git a/gas/testsuite/gas/i386/intelbad.l b/gas/testsuite/gas/i386/intelbad.l index 8f6341d150f..4d45dda36f7 100644 --- a/gas/testsuite/gas/i386/intelbad.l +++ b/gas/testsuite/gas/i386/intelbad.l @@ -161,11 +161,9 @@ .*:181: Error: .* .*:183: Error: .* .*:184: Error: .* -.*:186: Error: .* .*:187: Error: .* .*:188: Error: .* .*:189: Error: .* -.*:191: Error: .* .*:192: Error: .* .*:193: Error: .* .*:194: Error: .* diff --git a/gas/testsuite/gas/i386/intelbad.s b/gas/testsuite/gas/i386/intelbad.s index 77375579a47..3a9bcde47fa 100644 --- a/gas/testsuite/gas/i386/intelbad.s +++ b/gas/testsuite/gas/i386/intelbad.s @@ -183,12 +183,12 @@ start: fild far ptr [ebx] fist near ptr [ebx] - lar eax, ax + lar ax, eax lar eax, dword ptr [eax] lar ax, dword ptr [eax] - lsl eax, ax + lsl ax, eax lsl eax, dword ptr [eax] lsl ax, dword ptr [eax] diff --git a/gas/testsuite/gas/i386/x86_64-intel.d b/gas/testsuite/gas/i386/x86_64-intel.d index e40a2e56f9e..b919dc0e851 100644 --- a/gas/testsuite/gas/i386/x86_64-intel.d +++ b/gas/testsuite/gas/i386/x86_64-intel.d @@ -258,4 +258,36 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f c3 00 movnti QWORD PTR \[rax\],rax [ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov eax,DWORD PTR (ds:)?0x0 [ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov QWORD PTR (ds:)?0x0,rcx +[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,dx +[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 48 0f 02 12 lar rdx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,dx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 48 0f 03 12 lsl rdx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,dx +[ ]*[a-f0-9]+: 0f 02 d2 lar edx,dx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,dx +[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 48 0f 02 12 lar rdx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,dx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,dx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\] +[ ]*[a-f0-9]+: 48 0f 03 12 lsl rdx,WORD PTR \[rdx\] #pass diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d index 73c687350b7..398d2aa4b9e 100644 --- a/gas/testsuite/gas/i386/x86_64.d +++ b/gas/testsuite/gas/i386/x86_64.d @@ -258,4 +258,36 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\) [ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax [ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov %rcx,0x0 +[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar %dx,%rdx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar %dx,%rdx +[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx +[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx +[ ]*[a-f0-9]+: 48 0f 02 12 lar \(%rdx\),%rdx +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %dx,%rdx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %dx,%rdx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx +[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx +[ ]*[a-f0-9]+: 48 0f 03 12 lsl \(%rdx\),%rdx +[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar %dx,%rdx +[ ]*[a-f0-9]+: 0f 02 d2 lar %dx,%edx +[ ]*[a-f0-9]+: 48 0f 02 d2 lar %dx,%rdx +[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx +[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx +[ ]*[a-f0-9]+: 48 0f 02 12 lar \(%rdx\),%rdx +[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %dx,%rdx +[ ]*[a-f0-9]+: 0f 03 d2 lsl %dx,%edx +[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %dx,%rdx +[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx +[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx +[ ]*[a-f0-9]+: 48 0f 03 12 lsl \(%rdx\),%rdx #pass diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s index e050b14be36..7f58e161770 100644 --- a/gas/testsuite/gas/i386/x86_64.s +++ b/gas/testsuite/gas/i386/x86_64.s @@ -310,3 +310,39 @@ movnti qword ptr [rax], rax mov eax, tr1 mov tr0, rcx + + .att_syntax + lar %dx,%dx + lar %dx,%edx + lar %dx,%rdx + lar %edx,%edx + lar %rdx,%rdx + lar (%rdx),%dx + lar (%rdx),%edx + lar (%rdx),%rdx + lsl %dx,%dx + lsl %dx,%edx + lsl %dx,%rdx + lsl %edx,%edx + lsl %rdx,%rdx + lsl (%rdx),%dx + lsl (%rdx),%edx + lsl (%rdx),%rdx + + .intel_syntax noprefix + lar dx,dx + lar edx,dx + lar rdx,dx + lar edx,edx + lar rdx,rdx + lar dx,WORD PTR [rdx] + lar edx,WORD PTR [rdx] + lar rdx,WORD PTR [rdx] + lsl dx,dx + lsl edx,dx + lsl rdx,dx + lsl edx,edx + lsl rdx,rdx + lsl dx,WORD PTR [rdx] + lsl edx,WORD PTR [rdx] + lsl rdx,WORD PTR [rdx] diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index edc2ce96765..e43666af841 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -833,8 +833,6 @@ enum MOD_0F01_REG_3, MOD_0F01_REG_5, MOD_0F01_REG_7, - MOD_0F02, - MOD_0F03, MOD_0F12_PREFIX_0, MOD_0F12_PREFIX_2, MOD_0F13, @@ -2117,8 +2115,8 @@ static const struct dis386 dis386_twobyte[] = { /* 00 */ { REG_TABLE (REG_0F00 ) }, { REG_TABLE (REG_0F01 ) }, - { MOD_TABLE (MOD_0F02) }, - { MOD_TABLE (MOD_0F03) }, + { "larS", { Gv, Ew }, 0 }, + { "lslS", { Gv, Ew }, 0 }, { Bad_Opcode }, { "syscall", { XX }, 0 }, { "clts", { XX }, 0 }, @@ -8199,16 +8197,6 @@ static const struct dis386 mod_table[][2] = { { "invlpg", { Mb }, 0 }, { RM_TABLE (RM_0F01_REG_7_MOD_3) }, }, - { - /* MOD_0F02 */ - { "larS", { Gv, Mw }, 0 }, - { "larS", { Gv, Ev }, 0 }, - }, - { - /* MOD_0F03 */ - { "lslS", { Gv, Mw }, 0 }, - { "lslS", { Gv, Ev }, 0 }, - }, { /* MOD_0F12_PREFIX_0 */ { "movlpX", { XM, EXq }, 0 }, diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 3766f32fd5f..8c13f85708b 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -572,7 +572,7 @@ nop, 0x90, None, 0, NoSuf|RepPrefixOk, {} // Protection control. arpl, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex } lar, 0xf02, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } -lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } lgdt, 0xf01, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } lgdt, 0xf01, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } lidt, 0xf01, 3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } @@ -580,7 +580,7 @@ lidt, 0xf01, 3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Un lldt, 0xf00, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } lmsw, 0xf01, 6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } lsl, 0xf03, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } -lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } ltr, 0xf00, 3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } sgdt, 0xf01, 0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index e77addf5658..82861459eef 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -5344,7 +5344,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, @@ -5452,7 +5452,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } },