From: Jason Ekstrand Date: Wed, 22 May 2019 17:20:01 +0000 (-0500) Subject: intel/fs,vec4: Use g0 as the header for MFENCE X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=859de4a74857d2736f6e2dd9d2fd98b92bbc69d9;p=mesa.git intel/fs,vec4: Use g0 as the header for MFENCE We set header_present but then pass it some random garbage. Give it g0 instead. I'm not actually sure this does anything but g0 is the usual header data and this is what the windows driver does so it seems like a good idea. Reviewed-by: Kenneth Graunke --- diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index d8532a0ff6e..8ef953d5aa4 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -1113,6 +1113,7 @@ brw_untyped_surface_write(struct brw_codegen *p, void brw_memory_fence(struct brw_codegen *p, struct brw_reg dst, + struct brw_reg src, enum opcode send_op); void diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index a271621393d..181932705f3 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3037,6 +3037,7 @@ brw_set_memory_fence_message(struct brw_codegen *p, void brw_memory_fence(struct brw_codegen *p, struct brw_reg dst, + struct brw_reg src, enum opcode send_op) { const struct gen_device_info *devinfo = p->devinfo; @@ -3048,15 +3049,15 @@ brw_memory_fence(struct brw_codegen *p, brw_push_insn_state(p); brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_exec_size(p, BRW_EXECUTE_1); - dst = vec1(dst); + dst = retype(vec1(dst), BRW_REGISTER_TYPE_UW); + src = retype(vec1(src), BRW_REGISTER_TYPE_UD); /* Set dst as destination for dependency tracking, the MEMORY_FENCE * message doesn't write anything back. */ insn = next_insn(p, send_op); - dst = retype(dst, BRW_REGISTER_TYPE_UW); brw_set_dest(p, insn, dst); - brw_set_src0(p, insn, dst); + brw_set_src0(p, insn, src); brw_set_memory_fence_message(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE, commit_enable); @@ -3067,7 +3068,7 @@ brw_memory_fence(struct brw_codegen *p, */ insn = next_insn(p, send_op); brw_set_dest(p, insn, offset(dst, 1)); - brw_set_src0(p, insn, offset(dst, 1)); + brw_set_src0(p, insn, src); brw_set_memory_fence_message(p, insn, GEN6_SFID_DATAPORT_RENDER_CACHE, commit_enable); diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 84909f83fec..1149e98ecd6 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2071,13 +2071,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case SHADER_OPCODE_MEMORY_FENCE: - brw_memory_fence(p, dst, BRW_OPCODE_SEND); + brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND); break; case SHADER_OPCODE_INTERLOCK: assert(devinfo->gen >= 9); /* The interlock is basically a memory fence issued via sendc */ - brw_memory_fence(p, dst, BRW_OPCODE_SENDC); + brw_memory_fence(p, dst, src[0], BRW_OPCODE_SENDC); break; case SHADER_OPCODE_FIND_LIVE_CHANNEL: { diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 87edd9d1fe0..6856eca687a 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4273,7 +4273,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr case nir_intrinsic_memory_barrier: { const fs_builder ubld = bld.group(8, 0); const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2); - ubld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp) + ubld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp, brw_vec8_grf(0, 0)) ->size_written = 2 * REG_SIZE; break; } @@ -5074,9 +5074,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr const fs_builder ubld = bld.group(8, 0); const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2); - ubld.emit(SHADER_OPCODE_INTERLOCK, tmp)->size_written = 2 * - REG_SIZE; - + ubld.emit(SHADER_OPCODE_INTERLOCK, tmp, brw_vec8_grf(0, 0)) + ->size_written = 2 * REG_SIZE; break; } diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index b6d2a0aba80..38181bf1469 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1886,7 +1886,7 @@ generate_code(struct brw_codegen *p, break; case SHADER_OPCODE_MEMORY_FENCE: - brw_memory_fence(p, dst, BRW_OPCODE_SEND); + brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND); break; case SHADER_OPCODE_FIND_LIVE_CHANNEL: { diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 39f78fa98a8..acf16b59153 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -760,7 +760,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) const vec4_builder bld = vec4_builder(this).at_end().annotate(current_annotation, base_ir); const dst_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 2); - bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp) + bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp, brw_vec8_grf(0, 0)) ->size_written = 2 * REG_SIZE; break; }