From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 2 Mar 2020 15:42:16 +0000 (+0000)
Subject: annoying, see https://github.com/nmigen/nmigen/issues/302
X-Git-Tag: ls180-24jan2020~111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85a87c0ffdfb955926d37f7fc75ecf05e0cd2097;p=ieee754fpu.git

annoying, see https://github.com/nmigen/nmigen/issues/302
shift can no longer be signed, even if the amount is guaranteed signed
---

diff --git a/src/ieee754/fpcommon/msbhigh.py b/src/ieee754/fpcommon/msbhigh.py
index 3a29935a..811555bf 100644
--- a/src/ieee754/fpcommon/msbhigh.py
+++ b/src/ieee754/fpcommon/msbhigh.py
@@ -46,6 +46,8 @@ class FPMSBHigh(Elaboratable):
         # took a "reverse" argument.
 
         clz = Signal((len(self.e_out), True), reset_less=True)
+        # GRRR utterly irritating https://github.com/nmigen/nmigen/issues/302
+        uclz = Signal(len(self.e_out), reset_less=True)
         temp = Signal(mwid, reset_less=True)
         if self.loprop:
             temp_r = Signal(mwid, reset_less=True)
@@ -65,7 +67,8 @@ class FPMSBHigh(Elaboratable):
         m.d.comb += [
             pe.i.eq(self.m_in[::-1]),     # inverted
             clz.eq(limclz),          # count zeros from MSB down
-            temp.eq((self.m_in << clz)),  # shift mantissa UP
+            uclz.eq(limclz),         # *sigh*...
+            temp.eq((self.m_in << uclz)),  # shift mantissa UP
             self.e_out.eq(self.e_in - clz), # DECREASE exponent
         ]
         if self.loprop: