From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 Jul 2020 15:05:18 +0000 (+0100)
Subject: add a simple addis test (regression)
X-Git-Tag: div_pipeline~159
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85b0caabba4996517c03b57292188ff0df45a522;p=soc.git

add a simple addis test (regression)
---

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index f1265a3a..51d4e7a1 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -220,6 +220,13 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
+    def test_30_addis(self):
+        lst = [#"addi 0, 0, 5",
+               "addis 12, 0, 0",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [0, 12])
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
         initial_regs = [0] * 32