From: lkcl <lkcl@web>
Date: Mon, 15 May 2023 12:28:30 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85b4cd20b905601abf13d395a70adf1990ceeebb;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index c104b19d6..747d2dbca 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -68,7 +68,7 @@ Fields:
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
   than the normal 0..VL-1
 * **N** sets signed/unsigned saturation.
-* **RC1** as if Rc=1, enables access to `VLi`.
+* **RC1** as if Rc=1, on operations that do not have it (typically Logical)
 * **VLi** VL inclusive: in fail-first mode, the truncation of
   VL *includes* the current element at the failure point rather
   than excludes it from the count.