From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Mar 2022 11:28:37 +0000 (+0000)
Subject: adding in hyperram peripheral
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85bc9a58008aab99eb3e42e914ad1a66983919bc;p=ls2.git

adding in hyperram peripheral
---

diff --git a/src/ls2.py b/src/ls2.py
index 6ce9a73..05966db 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -20,7 +20,7 @@ from nmigen_stdio.serial import AsyncSerial
 
 # HyperRAM
 from nmigen_boards.resources.memory import HyperRAMResource
-from lambdasoc.periph.hyperram import HyperRAM
+from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, HyperRAMPHY
 
 from lambdasoc.periph.intc import GenericInterruptController
 from lambdasoc.periph.sram import SRAMPeripheral
@@ -250,9 +250,9 @@ class DDR3SoC(SoC, Elaboratable):
         #          |
         #       arbiter
         #          |
-        #   +---decoder----+--------+---------+
-        #   |      |       |        |         |
-        #  uart  XICS    CSRs     DRAM     XIP SPI
+        #   +---decoder----+--------+---------+-------+
+        #   |      |       |        |         |       |
+        #  uart  XICS    CSRs     DRAM     XIP SPI HyperRAM
 
         # set up wishbone bus arbiter and decoder. arbiter routes,
         # decoder maps local-relative addressed satellites to global addresses
@@ -405,6 +405,9 @@ class DDR3SoC(SoC, Elaboratable):
         # HyperRAM modules *plural*. Assumes using a Quad PMOD by Piotr
         # Esden, sold by 1bitsquared, only doing one CS_N enable at the
         # moment
+        if hyperram_pins is not None:
+            self.hyperram = HyperRAM(io=hyperram_pins, phy_kls=HyperRAMPHY)
+            self._decoder.add(self.hyperram.bus, addr=hyperram_addr)
 
         self.memory_map = self._decoder.bus.memory_map
 
@@ -462,6 +465,10 @@ class DDR3SoC(SoC, Elaboratable):
             # grrr, same problem with drambone: not WB4-pipe compliant
             comb += drambone.bus.stall.eq(drambone.bus.cyc & ~drambone.bus.ack)
 
+        # add hyperram module
+        if hasattr(self, "hyperram"):
+            m.submodules.hyperram = self.hyperram
+
         # add blinky lights so we know FPGA is alive
         if platform is not None:
             m.submodules.blinky = Blinky()
@@ -511,6 +518,8 @@ class DDR3SoC(SoC, Elaboratable):
         # and at the moment that's just UART tx/rx.
         ports = []
         ports += [self.uart.tx_o, self.uart.rx_i]
+        if hasattr(self, "hyperram"):
+            ports += list(self.hyperram.ports())
         if hasattr(self, "ddrphy"):
             if hasattr(self.ddrphy, "pads"): # real PHY
                 ports += list(self.ddrphy.pads.fields.values())
@@ -611,6 +620,8 @@ if __name__ == "__main__":
                                          attrs=IOStandard("LVCMOS33"))
         self.platform.add_extension(hyperram_ios)
         hyperram_pins = self.platform.request("hyperram")
+    else:
+        hyperram_pins = HyperRAMPads()
 
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,