From: Andrew Pinski Date: Wed, 14 Jun 2017 10:20:07 +0000 (+0000) Subject: re PR target/71663 (aarch64 Vector initialization can be improved slightly) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85c1b6d7c855fd1b76a385af2b7f2c56bf3b7f11;p=gcc.git re PR target/71663 (aarch64 Vector initialization can be improved slightly) PR target/71663 gcc * config/aarch64/aarch64.c (aarch64_expand_vector_init): Improve vector initialization code gen for only variable case. gcc/testsuite * gcc.target/aarch64/vect-init-1.c: Newtestcase. * gcc.target/aarch64/vect-init-2.c: Likewise. * gcc.target/aarch64/vect-init-3.c: Likewise. * gcc.target/aarch64/vect-init-4.c: Likewise. * gcc.target/aarch64/vect-init-5.c: Likewise. Co-Authored-By: Naveen H.S From-SVN: r249187 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5eb74648591..8205b0e984a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-14 Andrew Pinski + Naveen H.S + + PR target/71663 + * config/aarch64/aarch64.c (aarch64_expand_vector_init): + Improve vector initialization code gen for only variable case. + 2017-06-14 Eric Botcazou * config/sparc/driver-sparc.c (cpu_names): Add SPARC-T5 entry. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index bce490ff555..239ba72570f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11707,6 +11707,57 @@ aarch64_expand_vector_init (rtx target, rtx vals) return; } + enum insn_code icode = optab_handler (vec_set_optab, mode); + gcc_assert (icode != CODE_FOR_nothing); + + /* If there are only variable elements, try to optimize + the insertion using dup for the most common element + followed by insertions. */ + + /* The algorithm will fill matches[*][0] with the earliest matching element, + and matches[X][1] with the count of duplicate elements (if X is the + earliest element which has duplicates). */ + + if (n_var == n_elts && n_elts <= 16) + { + int matches[16][2] = {0}; + for (int i = 0; i < n_elts; i++) + { + for (int j = 0; j <= i; j++) + { + if (rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, j))) + { + matches[i][0] = j; + matches[j][1]++; + break; + } + } + } + int maxelement = 0; + int maxv = 0; + for (int i = 0; i < n_elts; i++) + if (matches[i][1] > maxv) + { + maxelement = i; + maxv = matches[i][1]; + } + + /* Create a duplicate of the most common element. */ + rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement)); + aarch64_emit_move (target, gen_rtx_VEC_DUPLICATE (mode, x)); + + /* Insert the rest. */ + for (int i = 0; i < n_elts; i++) + { + rtx x = XVECEXP (vals, 0, i); + if (matches[i][0] == maxelement) + continue; + x = copy_to_mode_reg (inner_mode, x); + emit_insn (GEN_FCN (icode) (target, x, GEN_INT (i))); + } + return; + } + /* Initialise a vector which is part-variable. We want to first try to build those lanes which are constant in the most efficient way we can. */ @@ -11740,10 +11791,6 @@ aarch64_expand_vector_init (rtx target, rtx vals) } /* Insert the variable lanes directly. */ - - enum insn_code icode = optab_handler (vec_set_optab, mode); - gcc_assert (icode != CODE_FOR_nothing); - for (int i = 0; i < n_elts; i++) { rtx x = XVECEXP (vals, 0, i); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0f5a2930038..a41cecf173d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2017-06-14 Andrew Pinski + Naveen H.S + + PR target/71663 + * gcc.target/aarch64/vect-init-1.c: Newtestcase. + * gcc.target/aarch64/vect-init-2.c: Likewise. + * gcc.target/aarch64/vect-init-3.c: Likewise. + * gcc.target/aarch64/vect-init-4.c: Likewise. + * gcc.target/aarch64/vect-init-5.c: Likewise. + 2017-06-14 Paolo Carlini PR c++/58541 diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-1.c b/gcc/testsuite/gcc.target/aarch64/vect-init-1.c new file mode 100644 index 00000000000..90ba3ae3b99 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float c, float d) +{ + return (vector float) { a, b, c, d }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-2.c b/gcc/testsuite/gcc.target/aarch64/vect-init-2.c new file mode 100644 index 00000000000..04446754cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float d) +{ + return (vector float) { a, b, a, d }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-3.c b/gcc/testsuite/gcc.target/aarch64/vect-init-3.c new file mode 100644 index 00000000000..b5822b7fcb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, a, b }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-4.c b/gcc/testsuite/gcc.target/aarch64/vect-init-4.c new file mode 100644 index 00000000000..09a00958f14 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, b, a }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-5.c b/gcc/testsuite/gcc.target/aarch64/vect-init-5.c new file mode 100644 index 00000000000..76d5502d54b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, a, a }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */