From: Andrew Reynolds <andrew.j.reynolds@gmail.com>
Date: Tue, 29 Sep 2020 00:54:25 +0000 (-0500)
Subject: Disable regression that is timing out (#5142)
X-Git-Tag: cvc5-1.0.0~2797
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85c509bc5c4005861f9c393931b426a776d4c0d6;p=cvc5.git

Disable regression that is timing out (#5142)

Seems to be timing out on 1/5 of our CI runs currently.
---

diff --git a/test/regress/CMakeLists.txt b/test/regress/CMakeLists.txt
index a5ed6dd09..257a70c80 100644
--- a/test/regress/CMakeLists.txt
+++ b/test/regress/CMakeLists.txt
@@ -835,7 +835,6 @@ set(regress_0_tests
   regress0/rels/rel_tc_2_1.cvc
   regress0/rels/rel_tc_3.cvc
   regress0/rels/rel_tc_3_1.cvc
-  regress0/rels/rel_tc_7.cvc
   regress0/rels/rel_tc_8.cvc
   regress0/rels/rel_tp_3_1.cvc
   regress0/rels/rel_tp_join_0.cvc
@@ -2379,6 +2378,8 @@ set(regression_disabled_tests
   regress0/quantifiers/qbv-test-invert-bvshl-0-neq.smt2
   regress0/quantifiers/qbv-test-invert-concat-0-neq.smt2
   regress0/quantifiers/qbv-test-invert-concat-1-neq.smt2
+  # times out on some CI configs after dt fact vs lemma update #5115
+  regress0/rels/rel_tc_7.cvc
   regress0/sets/mar2014/stacks0.hs.78.cvc4.smt2
   regress0/sets/setel-eq.smt2
   regress0/sets/sets-new.smt2