From: GCC Administrator Date: Fri, 29 Jan 2021 00:16:21 +0000 (+0000) Subject: Daily bump. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85d04a2ecb75fb67f2d72f0ff2a34cee92acd7b8;p=gcc.git Daily bump. --- diff --git a/contrib/ChangeLog b/contrib/ChangeLog index 9b7e4a76910..1efbbeeb8be 100644 --- a/contrib/ChangeLog +++ b/contrib/ChangeLog @@ -1,3 +1,8 @@ +2021-01-28 Eric Botcazou + + PR lto/85574 + * compare-lto: Deal with PE-COFF executables specifically. + 2021-01-14 Martin Liska * mklog.py: Fix infinite loop for unsupported files. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 70b8f0aa009..f0c0390ebb9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,109 @@ +2021-01-28 Marek Polacek + + PR c++/94775 + * stor-layout.c (finalize_type_size): If we reset TYPE_USER_ALIGN in + the main variant, maybe reset it in its variants too. + * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match. + (check_aligned_type): Check if TYPE_USER_ALIGN match. + +2021-01-28 Christophe Lyon + + PR target/98730 + * config/arm/arm.c (arm_rtx_costs_internal): Adjust cost of vector + of constant zero for comparisons. + +2021-01-28 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_mangle_decl_assembler_name): Add + support for mapping built-in function names for long double + built-in functions if long double is IEEE 128-bit. + +2021-01-28 Jonathan Wright + + * config/aarch64/aarch64-simd-builtins.def: Add [su]mlsl_n + builtin generator macros. + * config/aarch64/aarch64-simd.md (aarch64_mlsl_n): + Define. + * config/aarch64/arm_neon.h (vmlsl_n_s16): Use RTL builtin + instead of inline asm. + (vmlsl_n_s32): Likewise. + (vmlsl_n_u16): Likewise. + (vmlsl_n_u32): Likewise. + +2021-01-28 Jonathan Wright + + * config/aarch64/aarch64-simd-builtins.def: Add [su]mlal_n + builtin generator macros. + * config/aarch64/aarch64-simd.md (aarch64_mlal_n): + Define. + * config/aarch64/arm_neon.h (vmlal_n_s16): Use RTL builtin + instead of inline asm. + (vmlal_n_s32): Likewise. + (vmlal_n_u16): Likewise. + (vmlal_n_u32): Likewise. + +2021-01-28 Kyrylo Tkachov + + * config/aarch64/aarch64-simd-builtins.def (shrn2): Define + builtin. + * config/aarch64/aarch64-simd.md (aarch64_shrn2_insn_le): + Define. + (aarch64_shrn2_insn_be): Likewise. + (aarch64_shrn2): Likewise. + * config/aarch64/arm_neon.h (vshrn_high_n_s16): Reimlplement + using builtins. + (vshrn_high_n_s32): Likewise. + (vshrn_high_n_s64): Likewise. + (vshrn_high_n_u16): Likewise. + (vshrn_high_n_u32): Likewise. + (vshrn_high_n_u64): Likewise. + +2021-01-28 Kyrylo Tkachov + + * config/aarch64/aarch64-simd-builtins.def (shrn): Define + builtin. + * config/aarch64/aarch64-simd.md (aarch64_shrn_insn_le): + Define. + (aarch64_shrn_insn_be): Likewise. + (aarch64_shrn): Likewise. + * config/aarch64/arm_neon.h (vshrn_n_s16): Reimplement using + builtins. + (vshrn_n_s32): Likewise. + (vshrn_n_s64): Likewise. + (vshrn_n_u16): Likewise. + (vshrn_n_u32): Likewise. + (vshrn_n_u64): Likewise. + * config/aarch64/iterators.md (vn_mode): New mode attribute. + +2021-01-28 Richard Biener + + PR rtl-optimization/80960 + * dse.c (check_mem_read_rtx): Call get_addr on the + offsetted address. + +2021-01-28 Xionghu Luo + David Edelsohn + + PR target/98799 + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Don't generate VIEW_CONVERT_EXPR for fcode ALTIVEC_BUILTIN_VEC_INSERT + when -m32. + * config/rs6000/rs6000-protos.h (rs6000_expand_vector_set_var): + Delete. + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Remove the + wrapper call rs6000_expand_vector_set_var for cleanup. Call + rs6000_expand_vector_set_var_p9 and rs6000_expand_vector_set_var_p8 + directly. + (rs6000_expand_vector_set_var): Delete. + (rs6000_expand_vector_set_var_p9): Make static. + (rs6000_expand_vector_set_var_p8): Make static. + +2021-01-28 Xing GUO + + * common/config/riscv/riscv-common.c + (riscv_subset_list::parsing_subset_version): Fix -march option parsing + when `p` extension exists. + 2021-01-27 Vladimir N. Makarov PR rtl-optimization/97684 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 6f2e9366761..1cdaac43194 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20210128 +20210129 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index b57663dda60..fa67d1a783e 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,9 @@ +2021-01-28 Jakub Jelinek + + * c.opt (-std=c++2a, -std=c++20, -std=gnu++2a, -std=gnu++20): Remove + draft from description. + (-std=c++2b): Fix a pasto, 2020 -> 2023. + 2021-01-26 Paul Fee * c-common.h (cxx_dialect): Add cxx23 as a dialect. diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 252bda6c0b9..144ff952d45 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,28 @@ +2021-01-28 Jakub Jelinek + + PR c++/98841 + * typeck.c (build_x_indirect_ref): For *this, return current_class_ref. + +2021-01-28 Jakub Jelinek + + PR c++/33661 + PR c++/98847 + * decl.c (cp_finish_decl): For register vars with asmspec in templates + call set_user_assembler_name and set DECL_HARD_REGISTER. + * pt.c (tsubst_expr): When instantiating DECL_HARD_REGISTER vars, + pass asmspec_tree to cp_finish_decl. + +2021-01-28 Nathan Sidwell + + PR c++/98770 + * module.cc (trees_out::decl_value): Swap is_typedef & TYPE_NAME + check order. + (trees_in::decl_value): Do typedef frobbing only when installing + a new typedef, adjust is_matching_decl call. Swap is_typedef + & TYPE_NAME check. + (trees_in::is_matching_decl): Add is_typedef parm. Adjust variable + names and deal with typedef checking. + 2021-01-27 Jason Merrill PR c++/97874 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index ec26cea2ebc..560250369e3 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2021-01-28 Harald Anlauf + + PR fortran/86470 + * trans.c (gfc_call_malloc): Allocate area of size 1 if passed + size is NULL (as documented). + 2021-01-27 Paul Thomas PR fortran/93924 diff --git a/gcc/go/ChangeLog b/gcc/go/ChangeLog index 8a9e2823dae..85bd3435a18 100644 --- a/gcc/go/ChangeLog +++ b/gcc/go/ChangeLog @@ -1,3 +1,8 @@ +2021-01-28 Ian Lance Taylor + + * gospec.c (lang_specific_driver): Add -g if no debugging options + were passed. + 2021-01-15 Ian Lance Taylor * Make-lang.in (GO_OBJS): Add go/embed.o. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c985d48f797..37000934e92 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,77 @@ +2021-01-28 Jakub Jelinek + + PR c++/98841 + * g++.dg/warn/effc5.C: New test. + +2021-01-28 Marek Polacek + + PR c++/94775 + * g++.dg/cpp0x/alignas19.C: New test. + * g++.dg/warn/Warray-bounds15.C: New test. + +2021-01-28 Christophe Lyon + + PR target/98730 + * gcc.target/arm/simd/vceqzq_p64.c: Update expected result. + +2021-01-28 David Edelsohn + + * gfortran.dg/ISO_Fortran_binding_18.c: Include + ../../../libgfortran/ISO_Fortran_binding.h rather than + ISO_Fortran_binding.h. + +2021-01-28 Michael Meissner + + * gcc.target/powerpc/float128-longdouble-math.c: New test. + * gcc.target/powerpc/float128-longdouble-stdio.c: New test. + * gcc.target/powerpc/float128-math.c: Adjust test for new name + being generated. Add support for running test on power10. Add + support for running if long double defaults to 64-bits. + +2021-01-28 Jakub Jelinek + + PR c++/33661 + PR c++/98847 + * g++.target/i386/pr98847.C: New test. + +2021-01-28 Kyrylo Tkachov + + * gcc.target/aarch64/narrow_high-intrinsics.c: Fix shrn2 scan. + +2021-01-28 Nathan Sidwell + + PR c++/98770 + * g++.dg/modules/pr98770_a.C: New. + * g++.dg/modules/pr98770_b.C: New. + +2021-01-28 Harald Anlauf + + PR fortran/86470 + * gfortran.dg/gomp/pr86470.f90: New test. + +2021-01-28 Xionghu Luo + + PR target/98827 + * gcc.target/powerpc/fold-vec-insert-char-p8.c: Adjust ilp32. + * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-double.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise. + * gcc.target/powerpc/pr79251.p8.c: Likewise. + * gcc.target/powerpc/pr79251.p9.c: Likewise. + * gcc.target/powerpc/vsx-builtin-7.c: Likewise. + * gcc.target/powerpc/pr79251-run.c: Build and run with vsx + option. + +2021-01-28 Xing GUO + + * gcc.target/riscv/attribute-18.c: New test. + 2021-01-27 Harris Snyder * gfortran.dg/ISO_Fortran_binding_18.c: New test. diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 1d976faaafe..e7b7ed0c7ee 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,21 @@ +2021-01-28 Jonathan Wakely + + * include/experimental/bits/numeric_traits.h: Update copyright + dates. + * include/experimental/bits/simd.h: Likewise. + * include/experimental/bits/simd_builtin.h: Likewise. + * include/experimental/bits/simd_converter.h: Likewise. + * include/experimental/bits/simd_detail.h: Likewise. + * include/experimental/bits/simd_fixed_size.h: Likewise. + * include/experimental/bits/simd_math.h: Likewise. + * include/experimental/bits/simd_neon.h: Likewise. + * include/experimental/bits/simd_ppc.h: Likewise. + * include/experimental/bits/simd_scalar.h: Likewise. + * include/experimental/bits/simd_x86.h: Likewise. + * include/experimental/bits/simd_x86_conversions.h: Likewise. + * include/experimental/simd: Likewise. + * testsuite/experimental/simd/*: Likewise. + 2021-01-27 Jonathan Wakely * doc/xml/manual/status_cxx2017.xml: Replace invalid entity.