From: Nelson Chu <nelson.chu@sifive.com>
Date: Fri, 8 Jan 2021 12:04:13 +0000 (-0800)
Subject: ld: Just xfail riscv little endian targets for compressed1d.d test.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85e963f185884ffec4ed9577da9b9fbd028b62ee;p=binutils-gdb.git

ld: Just xfail riscv little endian targets for compressed1d.d test.

The sizes of compressed and uncompressed .debug_aranges are the same
for the riscv big endian targets, but different for the little endian
targets.  The compress rule is fine and isn't broken by riscv, just the
original compressed1d.d fails by accident.  Ideally, we should fill the
R_RISCV_ADD/SUB relocations when disabling relaxations in the assembler.
But before that, Jim already had written an alternative test compressed1d-alt
to relpace compressed1d.d for riscv, so we can only xfail the riscv little
endian targets in the short-term.

ld/
    * testsuite/ld-elf/elf.exp (riscv_little_endian): Added.  Return true
    if target is riscv little endian.  Otherwise, return false.
    * testsuite/ld-elf/compressed1d.d: Only xfail the riscv little endian
    targets by [riscv_little_endian].
---

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 688a4427e82..035e6aa3fdc 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,10 @@
+2021-01-19  Nelson Chu  <nelson.chu@sifive.com>
+
+	* testsuite/ld-elf/elf.exp (riscv_little_endian): Added.  Return true
+	if target is riscv little endian.  Otherwise, return false.
+	* testsuite/ld-elf/compressed1d.d: Only xfail the riscv little endian
+	targets by [riscv_little_endian].
+
 2021-01-18  Alan Modra  <amodra@gmail.com>
 
 	PR 26378
diff --git a/ld/testsuite/ld-elf/compressed1d.d b/ld/testsuite/ld-elf/compressed1d.d
index df7ce344507..9d891c1933f 100644
--- a/ld/testsuite/ld-elf/compressed1d.d
+++ b/ld/testsuite/ld-elf/compressed1d.d
@@ -3,10 +3,11 @@
 #ld: -r --compress-debug-sections=zlib-gnu
 #readelf: -SW
 #xfail: [uses_genelf]
-#xfail: riscv*-*-*
+#xfail: [riscv_little_endian]
 # Not all ELF targets use the elf.em emulation...
 # RISC-V has linker relaxations that delete code, so text label subtractions
-# do not get resolved at assembly time, which results in a compressed section.
+# do not get resolved at assembly time, which results in a compressed section
+# for little endian targets; but it is uncompressed for big endian targets.
 
 #failif
 #...
diff --git a/ld/testsuite/ld-elf/elf.exp b/ld/testsuite/ld-elf/elf.exp
index 7179cec61e6..e98bffc0c5f 100644
--- a/ld/testsuite/ld-elf/elf.exp
+++ b/ld/testsuite/ld-elf/elf.exp
@@ -25,6 +25,19 @@ if ![is_elf_format] {
     return
 }
 
+# Return true if target is riscv little endian.
+# xfail the riscv little endain targets for the compressed1d1 test;
+# The riscv big endian targets and others should pass.
+proc riscv_little_endian { } {
+    if { [istarget "riscv32-*-*"]
+	 || [istarget "riscv64-*-*"]
+	 || [istarget "riscv32le-*-*"]
+	 || [istarget "riscv64le-*-*"] } {
+	return 1
+    }
+    return 0
+}
+
 set old_ldflags $LDFLAGS
 if { [istarget spu*-*-*] } {
     set LDFLAGS "$LDFLAGS --local-store 0:0"