From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 14 Jun 2021 22:00:24 +0000 (+0100)
Subject: temporary move regs into range 0-31
X-Git-Tag: xlen-bcd~465
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85fced0877790a7eda2f58fdbf11e76009637800;p=openpower-isa.git

temporary move regs into range 0-31
---

diff --git a/media/audio/mp3/mp3_0_apply_window_float_basicsv.s b/media/audio/mp3/mp3_0_apply_window_float_basicsv.s
index 344e21a8..4d88e138 100644
--- a/media/audio/mp3/mp3_0_apply_window_float_basicsv.s
+++ b/media/audio/mp3/mp3_0_apply_window_float_basicsv.s
@@ -11,12 +11,18 @@
 .set out2, 10
 
 # SV ints, so we don't have to play with the stack
-.set win2, 32
+#.set win2, 32
+# for now... TODO, add 128 regs to simulator
+.set win2, 16
 
 # SV floats
-.set fv0, 32
-.set fv1, 40
-.set fv2, 48
+#.set fv0, 32
+#.set fv1, 40
+#.set fv2, 48
+# for now... TODO, add 128 regs to simulator
+.set fv0, 0
+.set fv1, 8
+.set fv2, 16
 
 # floats
 .set sum, 0
@@ -44,7 +50,7 @@ ff_mpadsp_apply_window_float_sv:
 	mulli 0, incr, 31
 	add out2, out, 0
 
-	# setvl 0, 0, 8, 1, 1 # setvli MVL=8, VL=8
+	setvl 0, 0, 8, 1, 1 # setvli MVL=8, VL=8
 	# sv.addi win2, win, 124
 
 	lfiwax sum, 0, 9 # zero it