From: Richard Henderson <rth@cygnus.com>
Date: Sat, 7 Aug 1999 06:38:33 +0000 (-0700)
Subject: alpha.md (movhi and movqi patterns): Correct predicate for !BWX.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8608bd5665de161880f36cd9f5b5698a0bd958f3;p=gcc.git

alpha.md (movhi and movqi patterns): Correct predicate for !BWX.

        * alpha.md (movhi and movqi patterns): Correct predicate for !BWX.
        Remove fp reg alternatives.

From-SVN: r28576
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 82b987c3e27..e0232f11ef9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Sat Aug  7 00:21:20 1999  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.md (movhi and movqi patterns): Correct predicate for !BWX.
+	Remove fp reg alternatives.
+	
 Sat Aug  7 00:06:54 1999  Jeffrey A Law  (law@cygnus.com)
 
 	* gcc.texi: Update bug reporting text.
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 4cb2b5b04ce..9fb35d90a4e 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -4156,20 +4156,19 @@
   [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
 
 (define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,f")
-	(match_operand:HI 1 "input_operand" "rJ,n,fJ"))]
+  [(set (match_operand:HI 0 "register_operand" "=r,r")
+	(match_operand:HI 1 "input_operand" "rJ,n"))]
   "! TARGET_BWX
    && (register_operand (operands[0], HImode)
        || register_operand (operands[1], HImode))"
   "@
    mov %r1,%0
-   lda %0,%L1
-   fmov %R1,%0"
-  [(set_attr "type" "ilog,iadd,fcpys")])
+   lda %0,%L1"
+  [(set_attr "type" "ilog,iadd")])
 
 (define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,f")
-	(match_operand:HI 1 "input_operand" "rJ,n,m,rJ,fJ"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
+	(match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
   "TARGET_BWX
    && (register_operand (operands[0], HImode)
        || reg_or_0_operand (operands[1], HImode))"
@@ -4177,25 +4176,23 @@
    mov %r1,%0
    lda %0,%L1
    ldwu %0,%1
-   stw %r1,%0
-   fmov %R1,%0"
-  [(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
+   stw %r1,%0"
+  [(set_attr "type" "ilog,iadd,ild,ist")])
 
 (define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,f")
-	(match_operand:QI 1 "input_operand" "rJ,n,fJ"))]
+  [(set (match_operand:QI 0 "register_operand" "=r,r")
+	(match_operand:QI 1 "input_operand" "rJ,n"))]
   "! TARGET_BWX
    && (register_operand (operands[0], QImode)
        || register_operand (operands[1], QImode))"
   "@
    mov %r1,%0
-   lda %0,%L1
-   fmov %R1,%0"
-  [(set_attr "type" "ilog,iadd,fcpys")])
+   lda %0,%L1"
+  [(set_attr "type" "ilog,iadd")])
 
 (define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,f")
-	(match_operand:QI 1 "input_operand" "rJ,n,m,rJ,fJ"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
+	(match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
   "TARGET_BWX
    && (register_operand (operands[0], QImode)
        || reg_or_0_operand (operands[1], QImode))"
@@ -4203,9 +4200,8 @@
    mov %r1,%0
    lda %0,%L1
    ldbu %0,%1
-   stb %r1,%0
-   fmov %R1,%0"
-  [(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
+   stb %r1,%0"
+  [(set_attr "type" "ilog,iadd,ild,ist")])
 
 ;; We do two major things here: handle mem->mem and construct long
 ;; constants.