From: Alan Lawrence Date: Tue, 8 Sep 2015 19:18:29 +0000 (+0000) Subject: [AArch64] Improve code generation for float16 vector code X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=862abc04beb0874f2e4352c44f28849a52c5c434;p=gcc.git [AArch64] Improve code generation for float16 vector code gcc/: * config/aarch64/aarch64-simd.md (aarch64_simd_dup, aarch64_dup_lane, aarch64_dup_lane_, aarch64_simd_vec_set, vec_set, vec_perm_const, vec_init, *aarch64_simd_ld1r, vec_extract): Add V4HF and V8HF variants to iterator. * config/aarch64/aarch64.c (aarch64_evpc_dup): Add V4HF and V8HF cases. * config/aarch64/iterators.md (VDQF_F16): New. (VSWAP_WIDTH, vswap_width_name): Add V4HF and V8HF cases. From-SVN: r227550 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cba40396020..f9203d70511 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2015-09-08 Alan Lawrence + + * config/aarch64/aarch64-simd.md (aarch64_simd_dup, + aarch64_dup_lane, aarch64_dup_lane_, + aarch64_simd_vec_set, vec_set, vec_perm_const, + vec_init, *aarch64_simd_ld1r, vec_extract): Add + V4HF and V8HF variants to iterator. + + * config/aarch64/aarch64.c (aarch64_evpc_dup): Add V4HF and V8HF cases. + + * config/aarch64/iterators.md (VDQF_F16): New. + (VSWAP_WIDTH, vswap_width_name): Add V4HF and V8HF cases. + 2015-09-08 Alan Lawrence * config/aarch64/arm_neon.h (vreinterpret_p8_f16, vreinterpret_p16_f16, diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 8bd4057c808..426bcb62427 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -53,18 +53,19 @@ ) (define_insn "aarch64_simd_dup" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (vec_duplicate:VDQF (match_operand: 1 "register_operand" "w")))] + [(set (match_operand:VDQF_F16 0 "register_operand" "=w") + (vec_duplicate:VDQF_F16 + (match_operand: 1 "register_operand" "w")))] "TARGET_SIMD" "dup\\t%0., %1.[0]" [(set_attr "type" "neon_dup")] ) (define_insn "aarch64_dup_lane" - [(set (match_operand:VALL 0 "register_operand" "=w") - (vec_duplicate:VALL + [(set (match_operand:VALL_F16 0 "register_operand" "=w") + (vec_duplicate:VALL_F16 (vec_select: - (match_operand:VALL 1 "register_operand" "w") + (match_operand:VALL_F16 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]) )))] "TARGET_SIMD" @@ -76,8 +77,8 @@ ) (define_insn "aarch64_dup_lane_" - [(set (match_operand:VALL 0 "register_operand" "=w") - (vec_duplicate:VALL + [(set (match_operand:VALL_F16 0 "register_operand" "=w") + (vec_duplicate:VALL_F16 (vec_select: (match_operand: 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]) @@ -834,11 +835,11 @@ ) (define_insn "aarch64_simd_vec_set" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (vec_merge:VDQF - (vec_duplicate:VDQF + [(set (match_operand:VDQF_F16 0 "register_operand" "=w") + (vec_merge:VDQF_F16 + (vec_duplicate:VDQF_F16 (match_operand: 1 "register_operand" "w")) - (match_operand:VDQF 3 "register_operand" "0") + (match_operand:VDQF_F16 3 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { @@ -851,7 +852,7 @@ ) (define_expand "vec_set" - [(match_operand:VDQF 0 "register_operand" "+w") + [(match_operand:VDQF_F16 0 "register_operand" "+w") (match_operand: 1 "register_operand" "w") (match_operand:SI 2 "immediate_operand" "")] "TARGET_SIMD" @@ -4670,9 +4671,9 @@ ;; vec_perm support (define_expand "vec_perm_const" - [(match_operand:VALL 0 "register_operand") - (match_operand:VALL 1 "register_operand") - (match_operand:VALL 2 "register_operand") + [(match_operand:VALL_F16 0 "register_operand") + (match_operand:VALL_F16 1 "register_operand") + (match_operand:VALL_F16 2 "register_operand") (match_operand: 3)] "TARGET_SIMD" { @@ -4936,7 +4937,7 @@ ;; Standard pattern name vec_init. (define_expand "vec_init" - [(match_operand:VALL 0 "register_operand" "") + [(match_operand:VALL_F16 0 "register_operand" "") (match_operand 1 "" "")] "TARGET_SIMD" { @@ -4945,8 +4946,8 @@ }) (define_insn "*aarch64_simd_ld1r" - [(set (match_operand:VALL 0 "register_operand" "=w") - (vec_duplicate:VALL + [(set (match_operand:VALL_F16 0 "register_operand" "=w") + (vec_duplicate:VALL_F16 (match_operand: 1 "aarch64_simd_struct_operand" "Utv")))] "TARGET_SIMD" "ld1r\\t{%0.}, %1" @@ -4993,7 +4994,7 @@ (define_expand "vec_extract" [(match_operand: 0 "aarch64_simd_nonimmediate_operand" "") - (match_operand:VALL 1 "register_operand" "") + (match_operand:VALL_F16 1 "register_operand" "") (match_operand:SI 2 "immediate_operand" "")] "TARGET_SIMD" { diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 79671705d77..feb7b28db1e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11906,6 +11906,8 @@ aarch64_evpc_dup (struct expand_vec_perm_d *d) case V4SImode: gen = gen_aarch64_dup_lanev4si; break; case V2SImode: gen = gen_aarch64_dup_lanev2si; break; case V2DImode: gen = gen_aarch64_dup_lanev2di; break; + case V8HFmode: gen = gen_aarch64_dup_lanev8hf; break; + case V4HFmode: gen = gen_aarch64_dup_lanev4hf; break; case V4SFmode: gen = gen_aarch64_dup_lanev4sf; break; case V2SFmode: gen = gen_aarch64_dup_lanev2sf; break; case V2DFmode: gen = gen_aarch64_dup_lanev2df; break; diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d7dfdc1ff25..0210602a840 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -82,7 +82,10 @@ ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) -;; Vector Float modes. +;; Vector Float modes suitable for moving, loading and storing. +(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF]) + +;; Vector Float modes, barring HF modes. (define_mode_iterator VDQF [V2SF V4SF V2DF]) ;; Vector Float modes, and DF. @@ -627,12 +630,14 @@ (V2SI "V4SI") (V4SI "V2SI") (DI "V2DI") (V2DI "DI") (V2SF "V4SF") (V4SF "V2SF") + (V4HF "V8HF") (V8HF "V4HF") (DF "V2DF") (V2DF "DF")]) (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") (V4HI "to_128") (V8HI "to_64") (V2SI "to_128") (V4SI "to_64") (DI "to_128") (V2DI "to_64") + (V4HF "to_128") (V8HF "to_64") (V2SF "to_128") (V4SF "to_64") (DF "to_128") (V2DF "to_64")])