From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 16 Jan 2020 15:20:25 +0000 (+0100)
Subject: cpu/vexriscv: use 32-bit signal for externalResetVector
X-Git-Tag: 24jan2021_ls180~736
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=862e784eaefa41a05d92caa132d73b25205ad74c;p=litex.git

cpu/vexriscv: use 32-bit signal for externalResetVector
---

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 100ce4be..08c2c8a2 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -238,7 +238,7 @@ class VexRiscv(CPU, AutoCSR):
     def set_reset_address(self, reset_address):
         assert not hasattr(self, "reset_address")
         self.reset_address = reset_address
-        self.cpu_params.update(i_externalResetVector=reset_address)
+        self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))
 
     def add_timer(self):
         self.submodules.timer = VexRiscvTimer()