From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Apr 2019 13:22:43 +0000 (+0100)
Subject: replace i_valid with valid_i
X-Git-Tag: ls180-24jan2020~1187
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=863928452b9714bc702867003cda2a8338440dc7;p=ieee754fpu.git

replace i_valid with valid_i
---

diff --git a/src/add/fpadd/pipeline.py b/src/add/fpadd/pipeline.py
index 6917b678..5e116b9f 100644
--- a/src/add/fpadd/pipeline.py
+++ b/src/add/fpadd/pipeline.py
@@ -26,8 +26,6 @@ class FPADDBasePipe(ControlBase):
         self.pipe2 = FPAddAlignSingleAdd(width, id_wid)
         self.pipe3 = FPNormToPack(width, id_wid)
 
-        self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
-
     def elaborate(self, platform):
         m = Module()
         m.submodules.scnorm = self.pipe1
diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index c061807c..699e83d7 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -580,7 +580,7 @@ class FPBase:
         """
         res = v.decode2(m)
         ack = Signal()
-        with m.If((op.ready_o) & (op.i_valid_test)):
+        with m.If((op.ready_o) & (op.valid_i_test)):
             m.next = next_state
             # op is latched in from FPNumIn class on same ack/stb
             m.d.comb += ack.eq(0)
diff --git a/src/add/fpcommon/getop.py b/src/add/fpcommon/getop.py
index d06aa2e4..b966ecbd 100644
--- a/src/add/fpcommon/getop.py
+++ b/src/add/fpcommon/getop.py
@@ -26,7 +26,7 @@ class FPGetOpMod(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
-                                       (self.in_op.i_valid_test))
+                                       (self.in_op.valid_i_test))
         m.submodules.get_op_in = self.in_op
         #m.submodules.get_op_out = self.out_op
         with m.If(self.out_decode):
@@ -145,7 +145,7 @@ class FPGet2Op(FPState):
     def trigger_setup(self, m, in_stb, in_ack):
         """ links stb/ack
         """
-        m.d.comb += self.mod.i_valid.eq(in_stb)
+        m.d.comb += self.mod.valid_i.eq(in_stb)
         m.d.comb += in_ack.eq(self.mod.ready_o)
 
     def setup(self, m, i):
diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index abdf42ff..14c01bed 100644
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -181,10 +181,10 @@ class CombMultiOutPipeline(MultiOutControlBase):
         mid = self.n_mux.m_id
 
         # temporaries
-        p_i_valid = Signal(reset_less=True)
+        p_valid_i = Signal(reset_less=True)
         pv = Signal(reset_less=True)
-        m.d.comb += p_i_valid.eq(self.p.i_valid_test)
-        m.d.comb += pv.eq(self.p.i_valid & self.p.ready_o)
+        m.d.comb += p_valid_i.eq(self.p.valid_i_test)
+        m.d.comb += pv.eq(self.p.valid_i & self.p.ready_o)
 
         # all outputs to next stages first initialised to zero (invalid)
         # the only output "active" is then selected by the muxid
@@ -192,7 +192,7 @@ class CombMultiOutPipeline(MultiOutControlBase):
             m.d.comb += self.n[i].o_valid.eq(0)
         data_valid = self.n[mid].o_valid
         m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].i_ready)
-        m.d.comb += data_valid.eq(p_i_valid | \
+        m.d.comb += data_valid.eq(p_valid_i | \
                                     (~self.n[mid].i_ready & data_valid))
         with m.If(pv):
             m.d.comb += eq(r_data, self.p.i_data)
@@ -234,20 +234,20 @@ class CombMultiInPipeline(MultiInControlBase):
         # need an array of buffer registers conforming to *input* spec
         r_data = []
         data_valid = []
-        p_i_valid = []
+        p_valid_i = []
         n_i_readyn = []
         p_len = len(self.p)
         for i in range(p_len):
             r = self.stage.ispec() # input type
             r_data.append(r)
             data_valid.append(Signal(name="data_valid", reset_less=True))
-            p_i_valid.append(Signal(name="p_i_valid", reset_less=True))
+            p_valid_i.append(Signal(name="p_valid_i", reset_less=True))
             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
             if hasattr(self.stage, "setup"):
                 self.stage.setup(m, r)
         if len(r_data) > 1:
             r_data = Array(r_data)
-            p_i_valid = Array(p_i_valid)
+            p_valid_i = Array(p_valid_i)
             n_i_readyn = Array(n_i_readyn)
             data_valid = Array(data_valid)
 
@@ -257,9 +257,9 @@ class CombMultiInPipeline(MultiInControlBase):
         for i in range(p_len):
             m.d.comb += data_valid[i].eq(0)
             m.d.comb += n_i_readyn[i].eq(1)
-            m.d.comb += p_i_valid[i].eq(0)
+            m.d.comb += p_valid_i[i].eq(0)
             m.d.comb += self.p[i].ready_o.eq(0)
-        m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
+        m.d.comb += p_valid_i[mid].eq(self.p_mux.active)
         m.d.comb += self.p[mid].ready_o.eq(~data_valid[mid] | self.n.i_ready)
         m.d.comb += n_i_readyn[mid].eq(nirn & data_valid[mid])
         anyvalid = Signal(i, reset_less=True)
@@ -268,12 +268,12 @@ class CombMultiInPipeline(MultiInControlBase):
             av.append(data_valid[i])
         anyvalid = Cat(*av)
         m.d.comb += self.n.o_valid.eq(anyvalid.bool())
-        m.d.comb += data_valid[mid].eq(p_i_valid[mid] | \
+        m.d.comb += data_valid[mid].eq(p_valid_i[mid] | \
                                     (n_i_readyn[mid] & data_valid[mid]))
 
         for i in range(p_len):
             vr = Signal(reset_less=True)
-            m.d.comb += vr.eq(self.p[i].i_valid & self.p[i].ready_o)
+            m.d.comb += vr.eq(self.p[i].valid_i & self.p[i].ready_o)
             with m.If(vr):
                 m.d.comb += eq(r_data[i], self.p[i].i_data)
 
@@ -313,9 +313,9 @@ class InputPriorityArbiter(Elaboratable):
         # connect priority encoder
         in_ready = []
         for i in range(self.num_rows):
-            p_i_valid = Signal(reset_less=True)
-            m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_test)
-            in_ready.append(p_i_valid)
+            p_valid_i = Signal(reset_less=True)
+            m.d.comb += p_valid_i.eq(self.pipe.p[i].valid_i_test)
+            in_ready.append(p_valid_i)
         m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids"
         m.d.comb += self.active.eq(~pe.n)   # encoder active (one input valid)
         m.d.comb += self.m_id.eq(pe.o)       # output one active input
diff --git a/src/add/queue.py b/src/add/queue.py
index 5e290a7c..cb9e98e5 100644
--- a/src/add/queue.py
+++ b/src/add/queue.py
@@ -64,7 +64,7 @@ class Queue(FIFOInterface, Elaboratable):
 
         # convenience names
         p_ready_o = self.writable
-        p_i_valid = self.we
+        p_valid_i = self.we
         enq_data = self.din
 
         n_o_valid = self.readable
@@ -93,7 +93,7 @@ class Queue(FIFOInterface, Elaboratable):
                      deq_max.eq(deq_ptr == self.depth - 1),
                      empty.eq(ptr_match & ~maybe_full),
                      full.eq(ptr_match & maybe_full),
-                     do_enq.eq(p_ready_o & p_i_valid), # write conditions ok
+                     do_enq.eq(p_ready_o & p_valid_i), # write conditions ok
                      do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
 
                      # set readable and writable (NOTE: see pipe mode below)
@@ -127,7 +127,7 @@ class Queue(FIFOInterface, Elaboratable):
         # this done combinatorially to give the exact same characteristics
         # as Memory "write-through"... without relying on a changing API
         if self.fwft:
-            with m.If(p_i_valid):
+            with m.If(p_valid_i):
                 m.d.comb += n_o_valid.eq(1)
             with m.If(empty):
                 m.d.comb += deq_data.eq(enq_data)
diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 4222e469..28a55996 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -131,7 +131,7 @@
     where data will flow on *every* clock when the conditions are right.
 
     input acceptance conditions are when:
-        * incoming previous-stage strobe (p.i_valid) is HIGH
+        * incoming previous-stage strobe (p.valid_i) is HIGH
         * outgoing previous-stage ready   (p.ready_o) is LOW
 
     output transmission conditions are when:
@@ -265,7 +265,7 @@ def _spec(fn, name=None):
 
 class PrevControl(Elaboratable):
     """ contains signals that come *from* the previous stage (both in and out)
-        * i_valid: previous stage indicating all incoming data is valid.
+        * valid_i: previous stage indicating all incoming data is valid.
                    may be a multi-bit signal, where all bits are required
                    to be asserted to indicate "valid".
         * ready_o: output to next stage indicating readiness to accept data
@@ -274,7 +274,7 @@ class PrevControl(Elaboratable):
 
     def __init__(self, i_width=1, stage_ctl=False):
         self.stage_ctl = stage_ctl
-        self.i_valid = Signal(i_width, name="p_i_valid") # prev   >>in  self
+        self.valid_i = Signal(i_width, name="p_valid_i") # prev   >>in  self
         self._ready_o = Signal(name="p_ready_o") # prev   <<out self
         self.i_data = None # XXX MUST BE ADDED BY USER
         if stage_ctl:
@@ -293,43 +293,43 @@ class PrevControl(Elaboratable):
         """ internal helper function to connect stage to an input source.
             do not use to connect stage-to-stage!
         """
-        i_valid = prev.i_valid if direct else prev.i_valid_test
+        valid_i = prev.valid_i if direct else prev.valid_i_test
         i_data = fn(prev.i_data) if fn is not None else prev.i_data
-        return [self.i_valid.eq(i_valid),
+        return [self.valid_i.eq(valid_i),
                 prev.ready_o.eq(self.ready_o),
                 eq(self.i_data, i_data),
                ]
 
     @property
-    def i_valid_test(self):
-        vlen = len(self.i_valid)
+    def valid_i_test(self):
+        vlen = len(self.valid_i)
         if vlen > 1:
-            # multi-bit case: valid only when i_valid is all 1s
-            all1s = Const(-1, (len(self.i_valid), False))
-            i_valid = (self.i_valid == all1s)
+            # multi-bit case: valid only when valid_i is all 1s
+            all1s = Const(-1, (len(self.valid_i), False))
+            valid_i = (self.valid_i == all1s)
         else:
-            # single-bit i_valid case
-            i_valid = self.i_valid
+            # single-bit valid_i case
+            valid_i = self.valid_i
 
         # when stage indicates not ready, incoming data
         # must "appear" to be not ready too
         if self.stage_ctl:
-            i_valid = i_valid & self.s_ready_o
+            valid_i = valid_i & self.s_ready_o
 
-        return i_valid
+        return valid_i
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.trigger.eq(self.i_valid_test & self.ready_o)
+        m.d.comb += self.trigger.eq(self.valid_i_test & self.ready_o)
         return m
 
     def eq(self, i):
         return [self.i_data.eq(i.i_data),
                 self.ready_o.eq(i.ready_o),
-                self.i_valid.eq(i.i_valid)]
+                self.valid_i.eq(i.valid_i)]
 
     def __iter__(self):
-        yield self.i_valid
+        yield self.valid_i
         yield self.ready_o
         if hasattr(self.i_data, "ports"):
             yield from self.i_data.ports()
@@ -368,7 +368,7 @@ class NextControl(Elaboratable):
             data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
             use this when connecting stage-to-stage
         """
-        return [nxt.i_valid.eq(self.o_valid),
+        return [nxt.valid_i.eq(self.o_valid),
                 self.i_ready.eq(nxt.ready_o),
                 eq(nxt.i_data, self.o_data),
                ]
@@ -801,7 +801,7 @@ class BufferedHandshake(ControlBase):
 
         Argument: stage.  see Stage API above
 
-        stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
+        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
         stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
@@ -835,12 +835,12 @@ class BufferedHandshake(ControlBase):
         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
         nir_por = Signal(reset_less=True)
         nir_por_n = Signal(reset_less=True)
-        p_i_valid = Signal(reset_less=True)
+        p_valid_i = Signal(reset_less=True)
         nir_novn = Signal(reset_less=True)
         nirn_novn = Signal(reset_less=True)
         por_pivn = Signal(reset_less=True)
         npnn = Signal(reset_less=True)
-        self.m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
+        self.m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
                      o_n_validn.eq(~self.n.o_valid),
                      n_i_ready.eq(self.n.i_ready_test),
                      nir_por.eq(n_i_ready & self.p._ready_o),
@@ -848,7 +848,7 @@ class BufferedHandshake(ControlBase):
                      nir_novn.eq(n_i_ready | o_n_validn),
                      nirn_novn.eq(~n_i_ready & o_n_validn),
                      npnn.eq(nir_por | nirn_novn),
-                     por_pivn.eq(self.p._ready_o & ~p_i_valid)
+                     por_pivn.eq(self.p._ready_o & ~p_valid_i)
         ]
 
         # store result of processing in combinatorial temporary
@@ -861,7 +861,7 @@ class BufferedHandshake(ControlBase):
         # data pass-through conditions
         with self.m.If(npnn):
             o_data = self._postprocess(result)
-            self.m.d.sync += [self.n.o_valid.eq(p_i_valid), # valid if p_valid
+            self.m.d.sync += [self.n.o_valid.eq(p_valid_i), # valid if p_valid
                               eq(self.n.o_data, o_data),    # update output
                              ]
         # buffer flush conditions (NOTE: can override data passthru conditions)
@@ -883,7 +883,7 @@ class SimpleHandshake(ControlBase):
 
         Argument: stage.  see Stage API above
 
-        stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
+        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
         stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
@@ -927,18 +927,18 @@ class SimpleHandshake(ControlBase):
 
         # establish some combinatorial temporaries
         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
-        p_i_valid_p_ready_o = Signal(reset_less=True)
-        p_i_valid = Signal(reset_less=True)
-        m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
+        p_valid_i_p_ready_o = Signal(reset_less=True)
+        p_valid_i = Signal(reset_less=True)
+        m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
                      n_i_ready.eq(self.n.i_ready_test),
-                     p_i_valid_p_ready_o.eq(p_i_valid & self.p.ready_o),
+                     p_valid_i_p_ready_o.eq(p_valid_i & self.p.ready_o),
         ]
 
         # store result of processing in combinatorial temporary
         m.d.comb += eq(result, self.stage.process(self.p.i_data))
 
         # previous valid and ready
-        with m.If(p_i_valid_p_ready_o):
+        with m.If(p_valid_i_p_ready_o):
             o_data = self._postprocess(result)
             m.d.sync += [r_busy.eq(1),      # output valid
                          eq(self.n.o_data, o_data), # update output
@@ -972,7 +972,7 @@ class UnbufferedPipeline(ControlBase):
 
         Argument: stage.  see Stage API, above
 
-        stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
+        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
         stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
@@ -1034,16 +1034,16 @@ class UnbufferedPipeline(ControlBase):
         r_data = _spec(self.stage.ospec, "r_tmp") # output type
 
         # some temporaries
-        p_i_valid = Signal(reset_less=True)
+        p_valid_i = Signal(reset_less=True)
         pv = Signal(reset_less=True)
         buf_full = Signal(reset_less=True)
-        m.d.comb += p_i_valid.eq(self.p.i_valid_test)
-        m.d.comb += pv.eq(self.p.i_valid & self.p.ready_o)
+        m.d.comb += p_valid_i.eq(self.p.valid_i_test)
+        m.d.comb += pv.eq(self.p.valid_i & self.p.ready_o)
         m.d.comb += buf_full.eq(~self.n.i_ready_test & data_valid)
 
         m.d.comb += self.n.o_valid.eq(data_valid)
         m.d.comb += self.p._ready_o.eq(~data_valid | self.n.i_ready_test)
-        m.d.sync += data_valid.eq(p_i_valid | buf_full)
+        m.d.sync += data_valid.eq(p_valid_i | buf_full)
 
         with m.If(pv):
             m.d.sync += eq(r_data, self.stage.process(self.p.i_data))
@@ -1066,7 +1066,7 @@ class UnbufferedPipeline2(ControlBase):
 
         Argument: stage.  see Stage API, above
 
-        stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
+        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
         stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |    |
@@ -1120,10 +1120,10 @@ class UnbufferedPipeline2(ControlBase):
         buf = _spec(self.stage.ospec, "r_tmp") # output type
 
         # some temporaries
-        p_i_valid = Signal(reset_less=True)
-        m.d.comb += p_i_valid.eq(self.p.i_valid_test)
+        p_valid_i = Signal(reset_less=True)
+        m.d.comb += p_valid_i.eq(self.p.valid_i_test)
 
-        m.d.comb += self.n.o_valid.eq(buf_full | p_i_valid)
+        m.d.comb += self.n.o_valid.eq(buf_full | p_valid_i)
         m.d.comb += self.p._ready_o.eq(~buf_full)
         m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
 
@@ -1185,13 +1185,13 @@ class PassThroughHandshake(ControlBase):
         r_data = _spec(self.stage.ospec, "r_tmp") # output type
 
         # temporaries
-        p_i_valid = Signal(reset_less=True)
+        p_valid_i = Signal(reset_less=True)
         pvr = Signal(reset_less=True)
-        m.d.comb += p_i_valid.eq(self.p.i_valid_test)
-        m.d.comb += pvr.eq(p_i_valid & self.p.ready_o)
+        m.d.comb += p_valid_i.eq(self.p.valid_i_test)
+        m.d.comb += pvr.eq(p_valid_i & self.p.ready_o)
 
         m.d.comb += self.p.ready_o.eq(~self.n.o_valid |  self.n.i_ready_test)
-        m.d.sync += self.n.o_valid.eq(p_i_valid       | ~self.p.ready_o)
+        m.d.sync += self.n.o_valid.eq(p_valid_i       | ~self.p.ready_o)
 
         odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
         m.d.sync += eq(r_data, odata)
@@ -1269,7 +1269,7 @@ class FIFOControl(ControlBase):
         # connect previous rdy/valid/data - do cat on i_data
         # NOTE: cannot do the PrevControl-looking trick because
         # of need to process the data.  shaaaame....
-        m.d.comb += [fifo.we.eq(self.p.i_valid_test),
+        m.d.comb += [fifo.we.eq(self.p.valid_i_test),
                      self.p.ready_o.eq(fifo.writable),
                      eq(fifo.din, cat(result)),
                    ]
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 2dae49ea..898007dc 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -54,7 +54,7 @@ def tbench(dut):
     #yield dut.i_p_rst.eq(0)
     yield dut.n.i_ready.eq(1)
     yield dut.p.i_data.eq(5)
-    yield dut.p.i_valid.eq(1)
+    yield dut.p.valid_i.eq(1)
     yield
 
     yield dut.p.i_data.eq(7)
@@ -67,7 +67,7 @@ def tbench(dut):
     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
     yield dut.p.i_data.eq(9)
     yield
-    yield dut.p.i_valid.eq(0)
+    yield dut.p.valid_i.eq(0)
     yield dut.p.i_data.eq(12)
     yield
     yield dut.p.i_data.eq(32)
@@ -90,7 +90,7 @@ def tbench2(dut):
     #yield dut.p.i_rst.eq(0)
     yield dut.n.i_ready.eq(1)
     yield dut.p.i_data.eq(5)
-    yield dut.p.i_valid.eq(1)
+    yield dut.p.valid_i.eq(1)
     yield
 
     yield dut.p.i_data.eq(7)
@@ -104,7 +104,7 @@ def tbench2(dut):
     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
     yield dut.p.i_data.eq(9)
     yield
-    yield dut.p.i_valid.eq(0)
+    yield dut.p.valid_i.eq(0)
     yield dut.p.i_data.eq(12)
     yield
     yield dut.p.i_data.eq(32)
@@ -146,11 +146,11 @@ class Test3:
                     yield
                     continue
                 if send and self.i != len(self.data):
-                    yield self.dut.p.i_valid.eq(1)
+                    yield self.dut.p.valid_i.eq(1)
                     yield self.dut.p.i_data.eq(self.data[self.i])
                     self.i += 1
                 else:
-                    yield self.dut.p.i_valid.eq(0)
+                    yield self.dut.p.valid_i.eq(0)
                 yield
 
     def rcv(self):
@@ -220,12 +220,12 @@ class Test5:
                     yield
                     continue
                 if send and self.i != len(self.data):
-                    yield self.dut.p.i_valid.eq(1)
+                    yield self.dut.p.valid_i.eq(1)
                     for v in self.dut.set_input(self.data[self.i]):
                         yield v
                     self.i += 1
                 else:
-                    yield self.dut.p.i_valid.eq(0)
+                    yield self.dut.p.valid_i.eq(0)
                 yield
 
     def rcv(self):
@@ -272,11 +272,11 @@ def tbench4(dut):
         o_p_ready = yield dut.p.ready_o
         if o_p_ready:
             if send and i != len(data):
-                yield dut.p.i_valid.eq(1)
+                yield dut.p.valid_i.eq(1)
                 yield dut.p.i_data.eq(data[i])
                 i += 1
             else:
-                yield dut.p.i_valid.eq(0)
+                yield dut.p.valid_i.eq(0)
         yield
         o_n_valid = yield dut.n.o_valid
         i_n_ready = yield dut.n.i_ready_test
@@ -1021,7 +1021,7 @@ if __name__ == '__main__':
         print ("test 2")
         dut = ExampleBufPipe2()
         run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
-        ports = [dut.p.i_valid, dut.n.i_ready,
+        ports = [dut.p.valid_i, dut.n.i_ready,
                  dut.n.o_valid, dut.p.ready_o] + \
                  [dut.p.i_data] + [dut.n.o_data]
         vl = rtlil.convert(dut, ports=ports)
@@ -1053,7 +1053,7 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_6)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
 
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              list(dut.p.i_data) + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1064,7 +1064,7 @@ if __name__ == '__main__':
     dut = ExampleAddRecordPipe()
     data=data_dict()
     test = Test5(dut, resultfn_7, data=data)
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o,
              dut.p.i_data.src1, dut.p.i_data.src2,
              dut.n.o_data.src1, dut.n.o_data.src2]
@@ -1081,7 +1081,7 @@ if __name__ == '__main__':
 
     print ("test 9")
     dut = ExampleBufPipeChain2()
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1113,7 +1113,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1125,7 +1125,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1137,7 +1137,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1149,7 +1149,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1161,7 +1161,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1173,7 +1173,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_identical, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1185,7 +1185,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1197,7 +1197,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_identical, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1209,7 +1209,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1221,7 +1221,7 @@ if __name__ == '__main__':
     data=data_2op()
     test = Test5(dut, resultfn_8, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
@@ -1234,7 +1234,7 @@ if __name__ == '__main__':
     data=data_2op()
     test = Test5(dut, resultfn_8, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
@@ -1246,7 +1246,7 @@ if __name__ == '__main__':
     dut = FIFOTestRecordAddStageControl()
     data=data_2op()
     test = Test5(dut, resultfn_8, data=data)
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
@@ -1260,7 +1260,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1272,7 +1272,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1284,7 +1284,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1296,7 +1296,7 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
-    ports = [dut.p.i_valid, dut.n.i_ready,
+    ports = [dut.p.valid_i, dut.n.i_ready,
              dut.n.o_valid, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
diff --git a/src/add/test_fpadd_pipe.py b/src/add/test_fpadd_pipe.py
index f718bf7c..a72244c4 100644
--- a/src/add/test_fpadd_pipe.py
+++ b/src/add/test_fpadd_pipe.py
@@ -38,7 +38,7 @@ class InputTest:
         for i in range(self.tlen):
             op1, op2 = self.di[mid][i]
             rs = dut.p[mid]
-            yield rs.i_valid.eq(1)
+            yield rs.valid_i.eq(1)
             yield rs.i_data.a.eq(op1)
             yield rs.i_data.b.eq(op2)
             yield rs.i_data.mid.eq(mid)
@@ -54,12 +54,12 @@ class InputTest:
             print ("send", mid, i, hex(op1), hex(op2), hex(res.bits),
                            fop1, fop2, res)
 
-            yield rs.i_valid.eq(0)
+            yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
             for i in range(randint(0, 3)):
                 yield
 
-        yield rs.i_valid.eq(0)
+        yield rs.valid_i.eq(0)
         yield
 
         print ("send ended", mid)
diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index f88d8f97..3ce8a96a 100644
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -99,7 +99,7 @@ class FPDIVPipe(ControlBase):
 
         # see if connecting to stb/ack works
         m.d.comb += self.p.ready_o.eq(self.fpdiv.in_a.ready_o)
-        m.d.comb += self.fpdiv.in_a.i_valid.eq(self.p.i_valid_test)
+        m.d.comb += self.fpdiv.in_a.valid_i.eq(self.p.valid_i_test)
 
         m.d.comb += self.n.o_valid.eq(self.fpdiv.out_z.o_valid)
         m.d.comb += self.fpdiv.out_z.i_ready.eq(self.n.i_ready_test)
diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index a62b7e93..9ebcd8a7 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -66,7 +66,7 @@ class InputTest:
         for i in range(self.tlen):
             op2 = self.di[mid][i]
             rs = dut.p[mid]
-            yield rs.i_valid.eq(1)
+            yield rs.valid_i.eq(1)
             yield rs.i_data.data.eq(op2)
             yield rs.i_data.idx.eq(i)
             yield rs.i_data.mid.eq(mid)
@@ -78,12 +78,12 @@ class InputTest:
 
             print ("send", mid, i, hex(op2))
 
-            yield rs.i_valid.eq(0)
+            yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
             for i in range(randint(0, 3)):
                 yield
 
-        yield rs.i_valid.eq(0)
+        yield rs.valid_i.eq(0)
         yield
 
         print ("send ended", mid)
@@ -157,7 +157,7 @@ class OutputTest:
             op2 = self.di[i][0]
             mid = self.di[i][1]
             rs = dut.p
-            yield rs.i_valid.eq(1)
+            yield rs.valid_i.eq(1)
             yield rs.i_data.data.eq(op2)
             yield rs.i_data.mid.eq(mid)
             yield
@@ -168,12 +168,12 @@ class OutputTest:
 
             print ("send", mid, i, hex(op2))
 
-            yield rs.i_valid.eq(0)
+            yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
             for i in range(randint(0, 3)):
                 yield
 
-        yield rs.i_valid.eq(0)
+        yield rs.valid_i.eq(0)
 
 
 class TestMuxOutPipe(CombMuxOutPipe):
diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index c3db79f7..ac25bbd2 100644
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -65,7 +65,7 @@ class OutputTest:
             op2 = self.di[i][0]
             mid = self.di[i][1]
             rs = dut.p
-            yield rs.i_valid.eq(1)
+            yield rs.valid_i.eq(1)
             yield rs.i_data.data.eq(op2)
             yield rs.i_data.mid.eq(mid)
             yield
@@ -76,12 +76,12 @@ class OutputTest:
 
             print ("send", mid, i, hex(op2))
 
-            yield rs.i_valid.eq(0)
+            yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
             for i in range(randint(0, 3)):
                 yield
 
-        yield rs.i_valid.eq(0)
+        yield rs.valid_i.eq(0)
 
     def rcv(self, mid):
         out_i = 0
@@ -139,7 +139,7 @@ class TestSyncToPriorityPipe(Elaboratable):
         return m
 
     def ports(self):
-        res = [self.p.i_valid, self.p.ready_o] + \
+        res = [self.p.valid_i, self.p.ready_o] + \
                 self.p.i_data.ports()
         for i in range(len(self.n)):
             res += [self.n[i].i_ready, self.n[i].o_valid] + \
diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 351fdf70..58848841 100644
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -131,7 +131,7 @@ class InputTest:
         for i in range(self.tlen):
             op2 = self.di[mid][i]
             rs = dut.p[mid]
-            yield rs.i_valid.eq(1)
+            yield rs.valid_i.eq(1)
             yield rs.i_data.data.eq(op2)
             yield rs.i_data.idx.eq(i)
             yield rs.i_data.mid.eq(mid)
@@ -143,12 +143,12 @@ class InputTest:
 
             print ("send", mid, i, hex(op2))
 
-            yield rs.i_valid.eq(0)
+            yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
             for i in range(randint(0, 3)):
                 yield
 
-        yield rs.i_valid.eq(0)
+        yield rs.valid_i.eq(0)
         ## wait random period of time before queueing another value
         #for i in range(randint(0, 3)):
         #    yield
diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py
index c5a1c6ee..c46e2391 100644
--- a/src/add/unit_test_single.py
+++ b/src/add/unit_test_single.py
@@ -41,7 +41,7 @@ def get_rs_case(dut, a, b, mid):
     out_z = dut.res[0]
     yield dut.ids.in_mid.eq(mid)
     yield in_a.v.eq(a)
-    yield in_a.i_valid.eq(1)
+    yield in_a.valid_i.eq(1)
     yield
     yield
     yield
@@ -49,16 +49,16 @@ def get_rs_case(dut, a, b, mid):
     a_ack = (yield in_a.ready_o)
     assert a_ack == 0
 
-    yield in_a.i_valid.eq(0)
+    yield in_a.valid_i.eq(0)
 
     yield in_b.v.eq(b)
-    yield in_b.i_valid.eq(1)
+    yield in_b.valid_i.eq(1)
     yield
     yield
     b_ack = (yield in_b.ready_o)
     assert b_ack == 0
 
-    yield in_b.i_valid.eq(0)
+    yield in_b.valid_i.eq(0)
 
     yield out_z.i_ready.eq(1)
 
@@ -87,7 +87,7 @@ def check_rs_case(dut, a, b, z, mid=None):
 def get_case(dut, a, b, mid):
     #yield dut.in_mid.eq(mid)
     yield dut.in_a.v.eq(a)
-    yield dut.in_a.i_valid_test.eq(1)
+    yield dut.in_a.valid_i_test.eq(1)
     yield
     yield
     yield
@@ -95,16 +95,16 @@ def get_case(dut, a, b, mid):
     a_ack = (yield dut.in_a.ready_o)
     assert a_ack == 0
 
-    yield dut.in_a.i_valid.eq(0)
+    yield dut.in_a.valid_i.eq(0)
 
     yield dut.in_b.v.eq(b)
-    yield dut.in_b.i_valid.eq(1)
+    yield dut.in_b.valid_i.eq(1)
     yield
     yield
     b_ack = (yield dut.in_b.ready_o)
     assert b_ack == 0
 
-    yield dut.in_b.i_valid.eq(0)
+    yield dut.in_b.valid_i.eq(0)
 
     yield dut.out_z.i_ready.eq(1)