From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 30 Oct 2015 12:58:03 +0000 (+0100)
Subject: Bugfix in Xilinx LUT mapping
X-Git-Tag: yosys-0.6~77
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=864808992be407a9b33f222fa5846f5cd5f149ea;p=yosys.git

Bugfix in Xilinx LUT mapping
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ee67beba7..fbcc96014 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass {
 
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
-			Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : ""));
+			Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 		}