From: Ilia Sergachev <ilia.sergachev@protonmail.ch>
Date: Mon, 20 Jul 2020 16:23:09 +0000 (+0200)
Subject: interconnect/csr_bus: fix paged access warning
X-Git-Tag: 24jan2021_ls180~73^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8656ea9b67393f6c6350d152658c46e302579256;p=litex.git

interconnect/csr_bus: fix paged access warning
---

diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py
index b91a458e..cded5ae2 100644
--- a/litex/soc/interconnect/csr_bus.py
+++ b/litex/soc/interconnect/csr_bus.py
@@ -100,7 +100,7 @@ class SRAM(Module):
         page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
         if page_bits:
             self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
-            printf("WARNING: SRAM CSR memory will requires paged access.")
+            print("WARNING: SRAM CSR memory will require paged access.")
         else:
             self._page = None
         if read_only is None: