From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 17 Jan 2015 19:46:52 +0000 (+0100)
Subject: Added support for memories to flatten (techmap)
X-Git-Tag: yosys-0.5~92
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8658eed52a59d5f25b734bc08e0c0a7f1497102e;p=yosys.git

Added support for memories to flatten (techmap)
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index b1a40b25e..521ac61a0 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -153,9 +153,6 @@ struct TechmapWorker
 
 	void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
 	{
-		if (tpl->memories.size() != 0)
-			log_error("Technology map yielded memories -> this is not supported.\n");
-
 		if (tpl->processes.size() != 0) {
 			log("Technology map yielded processes:\n");
 			for (auto &it : tpl->processes)
@@ -176,6 +173,22 @@ struct TechmapWorker
 					break;
 				}
 
+		dict<IdString, IdString> memory_renames;
+
+		for (auto &it : tpl->memories) {
+			std::string m_name = it.first.str();
+			apply_prefix(cell->name.str(), m_name);
+			RTLIL::Memory *m = new RTLIL::Memory;
+			m->name = m_name;
+			m->width = it.second->width;
+			m->start_offset = it.second->start_offset;
+			m->size = it.second->size;
+			m->attributes = it.second->attributes;
+			module->memories[m->name] = m;
+			memory_renames[it.first] = m->name;
+			design->select(module, m);
+		}
+
 		std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
 
 		for (auto &it : tpl->wires_) {
@@ -252,6 +265,12 @@ struct TechmapWorker
 				apply_prefix(cell->name.str(), it2.second, module);
 				port_signal_map.apply(it2.second);
 			}
+
+			if (c->type == "$memrd" || c->type == "$memwr") {
+				IdString memid = c->getParam("\\MEMID").decode_string();
+				log_assert(memory_renames.count(memid));
+				c->setParam("\\MEMID", Const(memory_renames[memid].str()));
+			}
 		}
 
 		for (auto &it : tpl->connections()) {