From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Jun 2020 15:33:05 +0000 (+0100)
Subject: add comments and start of elaborate
X-Git-Tag: div_pipeline~553
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8659afdb4b193189276e8450686d733bad8a1e52;p=soc.git

add comments and start of elaborate
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 1e85beae..09d0e5f1 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -128,6 +128,14 @@ class DualPortSplitter(Elaboratable):
 
     once that is done each pair of ports may be wired directly
     to the dual ports of L0CacheBuffer
+
+    The split is carried out so that, regardless of alignment or
+    mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
+    of the address, whilst outgoing PortInterface[1] takes
+    bit 4 == 1.
+
+    PortInterface *may* need to be changed so that the length is
+    a binary number (accepting values 1-16).
     """
     def __init__(self):
         self.outp = []
@@ -135,6 +143,9 @@ class DualPortSplitter(Elaboratable):
         self.outp[1] = PortInterface(name="outp_1")
         self.inp     = PortInterface(name="inp")
 
+    def elaborate(self, platform):
+        splitter = LDSTSplitter(64, 48, 4)
+
 
 class DataMergerRecord(Record):
     """