From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 18:45:12 +0000 (+0100)
Subject: store CR lut result in temporary
X-Git-Tag: div_pipeline~1014
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8677fd4ee0f0bad4977261b11643a543020e6752;p=soc.git

store CR lut result in temporary
---

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 00417651..2ec877e5 100644
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -108,8 +108,10 @@ class CRMainStage(PipeModBase):
 
                 # Use the two input bits to look up the result in the LUT
                 idx = Signal(2, reset_less=True)
+                lv = Signal(1, reset_less=True)
                 comb += idx.eq(Cat(cr_arr[bb], cr_arr[ba]))
-                comb += cr_out_arr[bt].eq(lut[idx])
+                comb += lv.eq(lut[idx])
+                comb += cr_out_arr[bt].eq(lv)
 
             ##### mtcrf #####
             with m.Case(InternalOp.OP_MTCRF):