From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 19:29:35 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~200
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8684b58bed2875ab67e9b12912d791f9d588f272;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

8684b58bed2875ab67e9b12912d791f9d588f272
diff --cc techlibs/xilinx/cells_sim.v
index 6049b4225,258999f18..3aa686e81
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -558,32 -381,53 +558,76 @@@ module FDSE_1 
  );
    parameter [0:0] INIT = 1'b1;
    initial Q <= INIT;
 -  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 +  wire \$currQ ;
 +  reg \$nextQ ;
 +  always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
 +`ifdef _ABC
 +  // `abc9' requires that complex flops be split into a combinatorial
 +  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
 +  //   In order to achieve clock-enable behaviour, the current value
 +  //   of the sequential output is required which Yosys will
 +  //   connect to the special `\$currQ' wire.
 +
 +  // Special signal indicating clock domain
 +  //   (used to partition the module so that `abc9' only performs
 +  //    sequential synthesis (reachability analysis) correctly on
 +  //    one domain at a time)
 +  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
 +  // Special signal indicating control domain
 +  //   (which, combined with this spell type, encodes to `abc9'
 +  //    which flops may be merged together)
 +  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
 +  always @* Q = \$nextQ ;
 +`else
 +  assign \$currQ = Q;
 +  always @(negedge C) Q <= \$nextQ ;
 +`endif
  endmodule
  
+ module LDCE (
+   output reg Q,
+   (* invertible_pin = "IS_CLR_INVERTED" *)
+   input CLR,
+   input D,
+   (* invertible_pin = "IS_G_INVERTED" *)
+   input G,
+   input GE
+ );
+   parameter [0:0] INIT = 1'b0;
+   parameter [0:0] IS_CLR_INVERTED = 1'b0;
+   parameter [0:0] IS_G_INVERTED = 1'b0;
+   parameter MSGON = "TRUE";
+   parameter XON = "TRUE";
+   initial Q = INIT;
+   wire clr = CLR ^ IS_CLR_INVERTED;
+   wire g = G ^ IS_G_INVERTED;
+   always @*
+     if (clr) Q = 1'b0;
+     else if (GE && g) Q = D;
+ endmodule
+ 
+ module LDPE (
+   output reg Q,
+   input D,
+   (* invertible_pin = "IS_G_INVERTED" *)
+   input G,
+   input GE,
+   (* invertible_pin = "IS_PRE_INVERTED" *)
+   input PRE
+ );
+   parameter [0:0] INIT = 1'b1;
+   parameter [0:0] IS_G_INVERTED = 1'b0;
+   parameter [0:0] IS_PRE_INVERTED = 1'b0;
+   parameter MSGON = "TRUE";
+   parameter XON = "TRUE";
+   initial Q = INIT;
+   wire g = G ^ IS_G_INVERTED;
+   wire pre = PRE ^ IS_PRE_INVERTED;
+   always @*
+     if (pre) Q = 1'b1;
+     else if (GE && g) Q = D;
+ endmodule
+ 
  module RAM32X1D (
    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
    (* abc_arrival=1153 *)