From: Doug Evans <dje@google.com>
Date: Wed, 1 Jul 1998 22:57:07 +0000 (+0000)
Subject: * sim/m32r/hw-trap.ms: New testcase.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8686807e307f09e535db905e19a4ad57c03111ff;p=binutils-gdb.git

* sim/m32r/hw-trap.ms: New testcase.
---

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index f958a2316a4..16834560948 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+Wed Jul  1 15:57:54 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* sim/m32r/hw-trap.ms: New testcase.
+
 start-sanitize-sky
 Wed Jun 24 19:09:03 1998  Frank Ch. Eigler  <fche@cygnus.com>
 
diff --git a/sim/testsuite/sim/m32r/.Sanitize b/sim/testsuite/sim/m32r/.Sanitize
index 53a2266dd66..3f4cd863864 100644
--- a/sim/testsuite/sim/m32r/.Sanitize
+++ b/sim/testsuite/sim/m32r/.Sanitize
@@ -163,7 +163,7 @@ xor.cgs
 xor3.cgs
 
 hello.ms
-
+hw-trap.ms
 
 Things-to-lose:
 
diff --git a/sim/testsuite/sim/m32r/hw-trap.ms b/sim/testsuite/sim/m32r/hw-trap.ms
new file mode 100644
index 00000000000..6961e4fe7d8
--- /dev/null
+++ b/sim/testsuite/sim/m32r/hw-trap.ms
@@ -0,0 +1,31 @@
+# output: pass
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+; construct bra trap2_handler in trap 2 slot
+	ld24 r0,#bra_insn
+	ld r0,@r0
+	ld24 r1,#trap2_handler
+	addi r1,#-0x48 ; pc relative address from trap 2 slot to handler
+	srai r1,#2
+	or r0,r1
+	ld24 r2,#0x48 ; address of trap 2 slot
+	st r0,@r2
+
+; perform trap
+	ldi r4,#0
+	trap #2
+	test_h_gr r4,42
+
+	pass
+
+; trap 2 handler
+trap2_handler:
+	ldi r4,#42
+	rte
+
+bra_insn:
+	bra.l 0