From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 12 Jun 2008 04:48:02 +0000 (-0400)
Subject: X86: Have all 8 machine check registers since the kernel assumes they're there.
X-Git-Tag: m5_2.0_beta6~163
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8688ef3fe523bf40a0b90d88fb986c25571b298a;p=gem5.git

X86: Have all 8 machine check registers since the kernel assumes they're there.
---

diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index 15ea0d77b..83ba3c0c5 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
  * All rights reserved.
  *
  * Redistribution and use of this software in source and binary forms,
@@ -183,6 +183,9 @@ namespace X86ISA
         MISCREG_MC2_CTL,
         MISCREG_MC3_CTL,
         MISCREG_MC4_CTL,
+        MISCREG_MC5_CTL,
+        MISCREG_MC6_CTL,
+        MISCREG_MC7_CTL,
 
         MISCREG_MC_STATUS_BASE,
         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
@@ -190,6 +193,9 @@ namespace X86ISA
         MISCREG_MC2_STATUS,
         MISCREG_MC3_STATUS,
         MISCREG_MC4_STATUS,
+        MISCREG_MC5_STATUS,
+        MISCREG_MC6_STATUS,
+        MISCREG_MC7_STATUS,
 
         MISCREG_MC_ADDR_BASE,
         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
@@ -197,6 +203,9 @@ namespace X86ISA
         MISCREG_MC2_ADDR,
         MISCREG_MC3_ADDR,
         MISCREG_MC4_ADDR,
+        MISCREG_MC5_ADDR,
+        MISCREG_MC6_ADDR,
+        MISCREG_MC7_ADDR,
 
         MISCREG_MC_MISC_BASE,
         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
@@ -204,6 +213,9 @@ namespace X86ISA
         MISCREG_MC2_MISC,
         MISCREG_MC3_MISC,
         MISCREG_MC4_MISC,
+        MISCREG_MC5_MISC,
+        MISCREG_MC6_MISC,
+        MISCREG_MC7_MISC,
 
         // Extended feature enable register
         MISCREG_EFER,
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index b6793245e..f5e214a88 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -358,6 +358,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
               case 0x410:
                 regNum = MISCREG_MC4_CTL;
                 break;
+              case 0x414:
+                regNum = MISCREG_MC5_CTL;
+                break;
+              case 0x418:
+                regNum = MISCREG_MC6_CTL;
+                break;
+              case 0x41C:
+                regNum = MISCREG_MC7_CTL;
+                break;
               case 0x401:
                 regNum = MISCREG_MC0_STATUS;
                 break;
@@ -373,6 +382,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
               case 0x411:
                 regNum = MISCREG_MC4_STATUS;
                 break;
+              case 0x415:
+                regNum = MISCREG_MC5_STATUS;
+                break;
+              case 0x419:
+                regNum = MISCREG_MC6_STATUS;
+                break;
+              case 0x41D:
+                regNum = MISCREG_MC7_STATUS;
+                break;
               case 0x402:
                 regNum = MISCREG_MC0_ADDR;
                 break;
@@ -388,6 +406,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
               case 0x412:
                 regNum = MISCREG_MC4_ADDR;
                 break;
+              case 0x416:
+                regNum = MISCREG_MC5_ADDR;
+                break;
+              case 0x41A:
+                regNum = MISCREG_MC6_ADDR;
+                break;
+              case 0x41E:
+                regNum = MISCREG_MC7_ADDR;
+                break;
               case 0x403:
                 regNum = MISCREG_MC0_MISC;
                 break;
@@ -403,6 +430,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
               case 0x413:
                 regNum = MISCREG_MC4_MISC;
                 break;
+              case 0x417:
+                regNum = MISCREG_MC5_MISC;
+                break;
+              case 0x41B:
+                regNum = MISCREG_MC6_MISC;
+                break;
+              case 0x41F:
+                regNum = MISCREG_MC7_MISC;
+                break;
               case 0xC0000080:
                 regNum = MISCREG_EFER;
                 break;