From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 16 Aug 2019 10:53:12 +0000 (+0100)
Subject: dev-arm: Add redistributor-stride property to GICv3
X-Git-Tag: v19.0.0.0~646
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=869053c8fa25fb58b70d59ccdd8e81825e5ee9e3;p=gem5.git

dev-arm: Add redistributor-stride property to GICv3

This is needed since by default the model is assuming a GICv4
memory layout.

Change-Id: Ic64e6a488cc1a43a56ce28f6d11b8868df102aa0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20248
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index d2e2ace3f..734299f50 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -237,6 +237,10 @@ class Gicv3(BaseGic):
         node.append(self._state.sizeCellsProperty())
         node.append(FdtProperty("interrupt-controller"))
 
+        redist_stride = 0x40000 if self.gicv4 else 0x20000
+        node.append(FdtPropertyWords("redistributor-stride",
+            state.sizeCells(redist_stride)))
+
         regs = (
             state.addrCells(self.dist_addr) +
             state.sizeCells(0x10000) +