From: lkcl <lkcl@web>
Date: Tue, 22 Dec 2020 04:09:44 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1052
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86b570ef7d4bbb329a06d4c699a0f8223fd90d4d;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index b000dd99f..7b7577c1c 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -196,11 +196,12 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
 
 ## RM-2P-1S1D
 
-| Field Name | Field bits | Description                                 |
-| Rdest_EXTRA3 | `8:10`     | extends Rdest                     |
-| Rsrc1_EXTRA3 | `11:13`    | extends Rsrc1                      |
-| MASK_SRC     | `14:16`    | Execution Mask for Source     |
-| ELWIDTH_SRC  | `17:18`    | Element Width for Source      |
+| Field Name | Field bits | Description                 |
+|------------|------------|----------------------------|
+| Rdest_EXTRA3 | `8:10`     | extends Rdest             |
+| Rsrc1_EXTRA3 | `11:13`    | extends Rsrc1             |
+| MASK_SRC     | `14:16`    | Execution Mask for Source |
+| ELWIDTH_SRC  | `17:18`    | Element Width for Source  |
 
 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing. 
 
@@ -211,7 +212,7 @@ and STORE operations.  see [[sv/ldst]] for detailed anslysis.
 
 RM-2P-2S1D:
 
-| Field Name | Field bits | Description                                 |
+| Field Name | Field bits | Description                     |
 |------------|------------|----------------------------|
 | Rdest_EXTRA2 | `8:9`   | extends Rdest (R\*\_EXTRA2 Encoding)   |
 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |