From: Robert Jordens <jordens@gmail.com>
Date: Tue, 3 Dec 2013 02:32:13 +0000 (-0700)
Subject: migen.fhdl.size: verify fslice for negative values
X-Git-Tag: 24jan2021_ls180~2099^2~403
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86ba9c8bbc676758f8c7af3756d69fb6d5faa891;p=litex.git

migen.fhdl.size: verify fslice for negative values
---

diff --git a/migen/fhdl/size.py b/migen/fhdl/size.py
index e771ccca..345c9c54 100644
--- a/migen/fhdl/size.py
+++ b/migen/fhdl/size.py
@@ -161,16 +161,20 @@ def fslice(v, s):
 
 	Examples
 	--------
-	>>> fslice(Signal(2), 1) #doctest: +ELLIPSIS
+	>>> fslice(f.Signal(2), 1) #doctest: +ELLIPSIS
 	<migen.fhdl.structure._Slice object at 0x...>
 	>>> bin(fslice(0b1101, slice(1, None, 2)))
 	'0b10'
+	>>> fslice(-1, slice(0, 4))
+	1
+	>>> fslice(-7, slice(None))
+	9
 	"""
 	if isinstance(v, (bool, int)):
 		if isinstance(s, int):
 			s = slice(s)
-		idx = range(*s.indices(flen(v)))
-		return sum(((v>>i) & 1) << j for j, i in enumerate(idx))
+		idx = range(*s.indices(bits_for(v)))
+		return sum(((v >> i) & 1) << j for j, i in enumerate(idx))
 	elif isinstance(v, f.Value):
 		return v[s]
 	else:
@@ -190,8 +194,8 @@ def freversed(v):
 
 	Examples
 	--------
-	>>> freversed(Signal(2)) #doctest: +ELLIPSIS
-	<migen.fhdl.structure._Slice object at 0x...>
+	>>> freversed(f.Signal(2)) #doctest: +ELLIPSIS
+	<migen.fhdl.structure.Cat object at 0x...>
 	>>> bin(freversed(0b1011))
 	'0b1101'
 	"""
diff --git a/migen/test/test_size.py b/migen/test/test_size.py
index 07b30524..a55ad430 100644
--- a/migen/test/test_size.py
+++ b/migen/test/test_size.py
@@ -32,6 +32,9 @@ class SignalSizeCase(unittest.TestCase):
 		fslice(self.s, sl)
 		self.assertEqual(fslice(self.i, sl), 15)
 		self.assertEqual(fslice(self.j, sl), 8)
+		self.assertEqual(fslice(-1, 9), 1)
+		self.assertEqual(fslice(-1, slice(0, 4)), 0b1)
+		self.assertEqual(fslice(-7, slice(0, None, 1)), 0b1001)
 
 	def test_fslice_type(self):
 		self.assertRaises(TypeError, fslice, [], 3)