From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 28 Nov 2023 21:03:43 +0000 (+0000)
Subject: bug #672: fixing pospopcount assembler
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86c81f50477401563db902d70f39f579fe8e387d;p=openpower-isa.git

bug #672: fixing pospopcount assembler

there is a lot going on here, this is pushing the boundaries of
what ISAcaller can do (or hasnt been asked to do... until now)
* gbbd (gather bits and bytes double) had to be added
* sw=8,dw=64 had to be fixed (XLEN is actually 64 there
  but source elements have to be ZERO-EXTENDED...)
* a bug in sv.addi/sw=8 was found
  https://bugs.libre-soc.org/show_bug.cgi?id=1221
* some changes to setvl have to be made/written (!)
* sv.bc in CTR-reduction mode needs to potentially be fixed
  or at least properly examined
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py
index d20a1359..53b4a296 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py
@@ -37,23 +37,28 @@ class PosPopCountTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(
             [
-                "mtspr 9, 3",                   # move r3 to CTR
-                "setvl. 0,0,8,0,1,1",           # set MVL=VL=8
-                "sv.addi *8, 0, 0",             # initialise r8-r15 to zero
+                "mtspr 9, 3",               # move r3 to CTR
+                "setvl. 0,0,8,0,1,1",       # set MVL=VL=8 and CR0 (Rc=1)
+                "sv.addi *8, 0, 0",         # initialise r8-r15 to zero
                 # VL = MIN(CTR,MAXVL=8), Rc=1 (CR0 set if CTR ends)
                 "setvl. 3,0,2,0,1,1",
                 # load VL bytes (update r4 addr) but compressed (dw=8)
-                "sv.lbzu/pi/dw=8 *16, 1(4)",   # should be /lf here as well
-                # bpermd performs the transpose (which gets us to positional..)
-                "bpermd 4,4",
+                "sv.lbzu/pi/dw=8 *8, 1(4)", # should be /lf here as well
+                # gather performs the transpose (which gets us to positional..)
+                "gbbd 8,8",
+                # now add each byte to the accumulator vector
+                "setvl 0,0,8,0,1,1",        # set MVL=VL=8, do NOT touch CR0
+                "sv.ori/sw=8 *24,*8,0",     # expand first
+                "sv.add *16,*16,*24",
                 # branch back if still CTR
-                "sv.bc/all 16, *0, -0x1c", # CTR mode, reduce VL by CTR
+                "sv.bc/all 16, *0, -0x30", # CTR mode, reduce VL by CTR
             ]
         )
         lst = list(lst)
 
         tst_array = [23,19,25,189,76,255,32,191,67,205,0,39,107]
-        tst_array = [1,2,3,4] #4,5,6,7,8,9] #8,9,10,11,12,13]
+        #tst_array = [1,2,3,4,5,6,7,8,9,10,11,12,13]
+        tst_array = [254] * 10
         initial_regs = [0] * 64
         initial_regs[3] = len(tst_array)
         initial_regs[4] = 16  # load address
@@ -69,6 +74,9 @@ class PosPopCountTestCase(FHDLTestCase):
         for i, c in enumerate(tst_array):
             write_byte(initial_mem, 16+i, c)
 
+        for i, c in enumerate(tst_array):
+            print ("array", i, bin(c), c)
+
         # now get the expected results: do a simple pospopcount
         expected = [0]*8
         for c in tst_array: