From: Sylvain Munaut <tnt@246tNt.com>
Date: Sat, 24 Nov 2018 17:49:23 +0000 (+0100)
Subject: Make return value of $clog2 signed
X-Git-Tag: yosys-0.9~394^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86ce43999eaed10c3b9d141bb2f66bf98ad45eb6;p=yosys.git

Make return value of $clog2 signed

As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index bb4c9735d..55abe165f 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1913,7 +1913,7 @@ skip_dynamic_range_lvalue_expansion:;
 					if (arg_value.bits.at(i) == RTLIL::State::S1)
 						result = i + 1;
 
-				newNode = mkconst_int(result, false);
+				newNode = mkconst_int(result, true);
 				goto apply_newNode;
 			}