From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 25 Jul 2023 03:34:22 +0000 (-0700)
Subject: fix set[n]bc[r]
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86d23dced36bf6ceb830035f3f224a4e9b266f23;p=openpower-isa.git

fix set[n]bc[r]
---

diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn
index 7dcefecf..61454907 100644
--- a/openpower/isa/sprset.mdwn
+++ b/openpower/isa/sprset.mdwn
@@ -183,7 +183,7 @@ X-Form
 
 Pseudo-code:
 
-    RT <- (CR[BI] = 1) ? 1 : 0
+    RT <- (CR[BI + 32] = 1) ? 1 : 0
 
 Special Registers Altered:
 
@@ -197,7 +197,7 @@ X-Form
 
 Pseudo-code:
 
-    RT <- (CR[BI] = 1) ? 0 : 1
+    RT <- (CR[BI + 32] = 1) ? 0 : 1
 
 Special Registers Altered:
 
@@ -211,7 +211,7 @@ X-Form
 
 Pseudo-code:
 
-    RT <- (CR[BI] = 1) ? -1 : 0
+    RT <- (CR[BI + 32] = 1) ? -1 : 0
 
 Special Registers Altered:
 
@@ -225,7 +225,7 @@ X-Form
 
 Pseudo-code:
 
-    RT <- (CR[BI] = 1) ? 0 : -1
+    RT <- (CR[BI + 32] = 1) ? 0 : -1
 
 Special Registers Altered:
 
diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index 76227ed5..8e11b843 100644
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -430,7 +430,7 @@
     BI (11:15)
          Field used to specify a bit in the CR to be tested by
          a Branch Conditional instruction.
-         Formats: B, XL
+         Formats: B, X, XL
     bm (21:25)
          Field used to specify the Bit-mask Mode for bmask
          Formats: BM2
diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index c019f40e..05ffce9e 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -164,10 +164,10 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0010111010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,prtyd,X,,,
 0b0010011010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,prtyw,X,,,
 0b0010000000,CR,OP_SETB,NONE,NONE,NONE,RT,BFA,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setb,X,,,
-0b0110000000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setbc,X,,,
-0b0110100000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setbcr,X,,,
-0b0111000000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setnbc,X,,,
-0b0111100000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setnbcr,X,,,
+0b0110000000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setbc,X,,0,
+0b0110100000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setbcr,X,,0,
+0b0111000000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setnbc,X,,0,
+0b0111100000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setnbcr,X,,0,
 0b0111110010,MMU,OP_TLBIE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,slbia,X,,,
 0b0000011011,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,sld,X,,,
 0b0000011000,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,slw,X,,,
diff --git a/src/openpower/test/cr/cr_cases.py b/src/openpower/test/cr/cr_cases.py
index 12541062..b48e3829 100644
--- a/src/openpower/test/cr/cr_cases.py
+++ b/src/openpower/test/cr/cr_cases.py
@@ -208,7 +208,7 @@ class CRTestCase(TestAccumulatorBase):
                 cr = hash_256(f"{mnemonic} {case_idx} r4") % 2**32
                 crregs = [(cr >> i) & 0xF for i in reversed(range(0, 32, 4))]
                 e = ExpectedState(pc=4, int_regs=gprs, crregs=crregs)
-                if bool(cr & (1 << 10)) != rev:
+                if bool(cr & (1 << (31 - 10))) != rev:
                     if negate:
                         e.intregs[3] = 2**64 - 1
                     else: