From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Jan 2022 21:33:39 +0000 (+0000)
Subject: remove read of SRR1 for TRAP pipeline, pass via LDSTException
X-Git-Tag: sv_maxu_works-initial~535
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86dae5ad8d1b521416e1eb066a6f6ffe290faf81;p=openpower-isa.git

remove read of SRR1 for TRAP pipeline, pass via LDSTException
---

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index a0e87d19..b43f317e 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1582,12 +1582,6 @@ class PowerDecode2(PowerDecodeSubset):
         # Note: OP_SC could actually be modified to just be a trap
         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
                   (do_out.insn_type == MicrOp.OP_SC)):
-            # see fu/trap/main_stage.py trap() function: some bits of SRR1
-            # need to be preserved, rather than just blithely overwrite MSR.
-            # following microwatt, here.
-            # TRAP read fast2 = SRR1
-            comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
-            comb += e_out.read_fast2.ok.eq(1)
             # TRAP write fast1 = SRR0
             comb += e_out.write_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
             comb += e_out.write_fast1.ok.eq(1)