From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Fri, 13 Sep 2013 10:26:34 +0000 (+0000)
Subject: arm.md (arm_cmpsi_insn): Split rI alternative.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86eb4bd7266d96a6eee4776cab54da2f045a82d8;p=gcc.git

arm.md (arm_cmpsi_insn): Split rI alternative.

2013-09-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (arm_cmpsi_insn): Split rI alternative.
	Set type attribute correctly. Set predicable_short_it attribute.
	(cmpsi_shiftsi): Remove %? from output template.

From-SVN: r202560
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ba2929930ed..6d8c030f9da 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2013-09-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/arm/arm.md (arm_cmpsi_insn): Split rI alternative.
+	Set type attribute correctly. Set predicable_short_it attribute.
+	(cmpsi_shiftsi): Remove %? from output template.
+
 2013-09-13  Richard Biener  <rguenther@suse.de>
 
 	* tree-loop-distribution.c (struct rdg_component,
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 0f958041d7c..b094cff0d7e 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8239,19 +8239,21 @@
 
 (define_insn "*arm_cmpsi_insn"
   [(set (reg:CC CC_REGNUM)
-	(compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r")
-		    (match_operand:SI 1 "arm_add_operand"    "Py,r,rI,L")))]
+	(compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r,r")
+		    (match_operand:SI 1 "arm_add_operand"    "Py,r,r,I,L")))]
   "TARGET_32BIT"
   "@
    cmp%?\\t%0, %1
    cmp%?\\t%0, %1
    cmp%?\\t%0, %1
+   cmp%?\\t%0, %1
    cmn%?\\t%0, #%n1"
   [(set_attr "conds" "set")
-   (set_attr "arch" "t2,t2,any,any")
-   (set_attr "length" "2,2,4,4")
+   (set_attr "arch" "t2,t2,any,any,any")
+   (set_attr "length" "2,2,4,4,4")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alus_reg,alus_reg,alus_reg,alus_imm")]
+   (set_attr "predicable_short_it" "yes,yes,yes,no,no")
+   (set_attr "type" "alus_imm,alus_reg,alus_reg,alus_imm,alus_imm")]
 )
 
 (define_insn "*cmpsi_shiftsi"
@@ -8261,7 +8263,7 @@
 		     [(match_operand:SI 1 "s_register_operand" "r,r,r")
 		      (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))]
   "TARGET_32BIT"
-  "cmp%?\\t%0, %1%S3"
+  "cmp\\t%0, %1%S3"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
    (set_attr "arch" "32,a,a")