From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Fri, 30 Aug 2019 09:38:28 +0000 (+0300)
Subject: Fix test for counter
X-Git-Tag: working-ls180~1084^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86f1375ecd3e6721a0e5da469672db890926914e;p=yosys.git

Fix test for counter
---

diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys
index fb32e67a5..c65c21622 100644
--- a/tests/ice40/counter.ys
+++ b/tests/ice40/counter.ys
@@ -5,7 +5,7 @@ flatten
 equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 7 t:SB_CARRY
+select -assert-count 6 t:SB_CARRY
 select -assert-count 8 t:SB_DFFR
 select -assert-count 8 t:SB_LUT4
 select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D