From: whitequark <whitequark@whitequark.org>
Date: Sat, 11 Dec 2021 12:01:52 +0000 (+0000)
Subject: write_verilog: dump zero width sigspecs correctly.
X-Git-Tag: yosys-0.13~37^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86f2804dc3f80cd74349c62888376c8596fb1856;p=yosys.git

write_verilog: dump zero width sigspecs correctly.

Before this commit, zero width sigspecs were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

PR #1203 has addressed this issue before, but in an incomplete way.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 47ef1c479..13c78c526 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -358,7 +358,8 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
 void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 {
 	if (GetSize(sig) == 0) {
-		f << "\"\"";
+		// See IEEE 1364-2005 Clause 5.1.14.
+		f << "{0{1'b0}}";
 		return;
 	}
 	if (sig.is_chunk()) {