From: Sebastien Bourdeauducq Date: Thu, 10 Sep 2015 17:53:15 +0000 (-0700) Subject: mibuild -> migen.build X-Git-Tag: 24jan2021_ls180~2099^2~3^2~112 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86f34e82c354fdbfb0317862d0d9fc0a195ba9c4;p=litex.git mibuild -> migen.build --- diff --git a/README.md b/README.md index 960f0775..e90a59f3 100644 --- a/README.md +++ b/README.md @@ -48,7 +48,7 @@ http://m-labs.hk/gateware.html ```python from migen.fhdl.std import * -from mibuild.platforms import m1 +from migen.build.platforms import m1 plat = m1.Platform() led = plat.request("user_led") m = Module() diff --git a/doc/conf.py b/doc/conf.py index 9bac6059..fc7f1180 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -90,7 +90,7 @@ exclude_patterns = ['_build'] pygments_style = 'sphinx' # A list of ignored prefixes for module index sorting. -modindex_common_prefix = ['migen.', 'mibuild.'] +modindex_common_prefix = ['migen.'] numpydoc_show_class_members = False diff --git a/mibuild/__init__.py b/mibuild/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/mibuild/altera/__init__.py b/mibuild/altera/__init__.py deleted file mode 100644 index 9a084580..00000000 --- a/mibuild/altera/__init__.py +++ /dev/null @@ -1,2 +0,0 @@ -from mibuild.altera.platform import AlteraPlatform -from mibuild.altera.programmer import USBBlaster diff --git a/mibuild/altera/common.py b/mibuild/altera/common.py deleted file mode 100644 index 56e20655..00000000 --- a/mibuild/altera/common.py +++ /dev/null @@ -1,38 +0,0 @@ -from migen.fhdl.std import Instance, Module -from migen.genlib.io import DifferentialInput, DifferentialOutput - - -class QuartusDifferentialInputImpl(Module): - def __init__(self, i_p, i_n, o): - self.specials += Instance("ALT_INBUF_DIFF", - name="ibuf_diff", - i_i=i_p, - i_ibar=i_n, - o_o=o) - - -class QuartusDifferentialInput: - @staticmethod - def lower(dr): - return QuartusDifferentialInputImpl(dr.i_p, dr.i_n, dr.o) - - -class QuartusDifferentialOutputImpl(Module): - def __init__(self, i, o_p, o_n): - self.specials += Instance("ALT_OUTBUF_DIFF", - name="obuf_diff", - i_i=i, - o_o=o_p, - o_obar=o_n) - - -class QuartusDifferentialOutput: - @staticmethod - def lower(dr): - return QuartusDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) - - -altera_special_overrides = { - DifferentialInput: QuartusDifferentialInput, - DifferentialOutput: QuartusDifferentialOutput -} diff --git a/mibuild/altera/platform.py b/mibuild/altera/platform.py deleted file mode 100644 index 1cbf2a19..00000000 --- a/mibuild/altera/platform.py +++ /dev/null @@ -1,27 +0,0 @@ -from mibuild.generic_platform import GenericPlatform -from mibuild.altera import common, quartus - - -class AlteraPlatform(GenericPlatform): - bitstream_ext = ".sof" - - def __init__(self, *args, toolchain="quartus", **kwargs): - GenericPlatform.__init__(self, *args, **kwargs) - if toolchain == "quartus": - self.toolchain = quartus.AlteraQuartusToolchain() - else: - raise ValueError("Unknown toolchain") - - def get_verilog(self, *args, special_overrides=dict(), **kwargs): - so = dict(common.altera_special_overrides) - so.update(special_overrides) - return GenericPlatform.get_verilog(self, *args, special_overrides=so, - **kwargs) - - def build(self, *args, **kwargs): - return self.toolchain.build(self, *args, **kwargs) - - def add_period_constraint(self, clk, period): - if hasattr(clk, "p"): - clk = clk.p - self.toolchain.add_period_constraint(self, clk, period) diff --git a/mibuild/altera/programmer.py b/mibuild/altera/programmer.py deleted file mode 100644 index 77a24cc0..00000000 --- a/mibuild/altera/programmer.py +++ /dev/null @@ -1,13 +0,0 @@ -import subprocess - -from mibuild.generic_programmer import GenericProgrammer - - -class USBBlaster(GenericProgrammer): - needs_bitreverse = False - - def load_bitstream(self, bitstream_file, port=0): - usb_port = "[USB-{}]".format(port) - subprocess.call(["quartus_pgm", "-m", "jtag", "-c", - "USB-Blaster{}".format(usb_port), "-o", - "p;{}".format(bitstream_file)]) diff --git a/mibuild/altera/quartus.py b/mibuild/altera/quartus.py deleted file mode 100644 index ad5f50b1..00000000 --- a/mibuild/altera/quartus.py +++ /dev/null @@ -1,149 +0,0 @@ -# This file is Copyright (c) 2013 Florent Kermarrec -# License: BSD - -import os -import subprocess - -from migen.fhdl.structure import _Fragment -from mibuild.generic_platform import (Pins, IOStandard, Misc) - -from mibuild import tools - - -def _format_constraint(c, signame, fmt_r): - if isinstance(c, Pins): - return "set_location_assignment -comment \"{name}\" " \ - "-to {signame} Pin_{pin}".format( - signame=signame, - name=fmt_r, - pin=c.identifiers[0]) - elif isinstance(c, IOStandard): - return "set_instance_assignment -name io_standard " \ - "-comment \"{name}\" \"{std}\" -to {signame}".format( - signame=signame, - name=fmt_r, - std=c.name) - elif isinstance(c, Misc): - if not isinstance(c.misc, str) and len(c.misc) == 2: - return "set_instance_assignment -comment \"{name}\" " \ - "-name {misc[0]} \"{misc[1]}\" -to {signame}".format( - signame=signame, - name=fmt_r, - misc=c.misc) - else: - return "set_instance_assignment -comment \"{name}\" " \ - "-name {misc} " \ - "-to {signame}".format( - signame=signame, - name=fmt_r, - misc=c.misc) - - -def _format_qsf(signame, pin, others, resname): - fmt_r = "{}:{}".format(*resname[:2]) - if resname[2] is not None: - fmt_r += "." + resname[2] - - fmt_c = [_format_constraint(c, signame, fmt_r) for c in - ([Pins(pin)] + others)] - - return '\n'.join(fmt_c) - - -def _build_qsf(named_sc, named_pc): - lines = [] - for sig, pins, others, resname in named_sc: - if len(pins) > 1: - for i, p in enumerate(pins): - lines.append( - _format_qsf("{}[{}]".format(sig, i), p, others, resname)) - else: - lines.append(_format_qsf(sig, pins[0], others, resname)) - - if named_pc: - lines.append("") - lines.append("\n\n".join(named_pc)) - - lines.append("set_global_assignment -name top_level_entity top") - return "\n".join(lines) - - -def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name): - lines = [] - for filename, language, library in sources: - # Enforce use of SystemVerilog - # (Quartus does not support global parameters in Verilog) - if language == "verilog": - language = "systemverilog" - lines.append( - "set_global_assignment -name {lang}_FILE {path} " - "-library {lib}".format( - lang=language.upper(), - path=filename.replace("\\", "/"), - lib=library)) - - for path in vincpaths: - lines.append("set_global_assignment -name SEARCH_PATH {}".format( - path.replace("\\", "/"))) - - lines.append(_build_qsf(named_sc, named_pc)) - lines.append("set_global_assignment -name DEVICE {}".format(device)) - tools.write_to_file("{}.qsf".format(build_name), "\n".join(lines)) - - -def _run_quartus(build_name, quartus_path): - build_script_contents = """# Autogenerated by mibuild - -quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name} -quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name} -quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name} -quartus_sta {build_name} -c {build_name} - -""".format(build_name=build_name) # noqa - build_script_file = "build_" + build_name + ".sh" - tools.write_to_file(build_script_file, - build_script_contents, - force_unix=True) - - if subprocess.call(["bash", build_script_file]): - raise OSError("Subprocess failed") - - -class AlteraQuartusToolchain: - def build(self, platform, fragment, build_dir="build", build_name="top", - quartus_path="/opt/Altera", run=True): - tools.mkdir_noerror(build_dir) - os.chdir(build_dir) - - if not isinstance(fragment, _Fragment): - fragment = fragment.get_fragment() - platform.finalize(fragment) - - v_output = platform.get_verilog(fragment) - named_sc, named_pc = platform.resolve_signals(v_output.ns) - v_file = build_name + ".v" - v_output.write(v_file) - sources = platform.sources | {(v_file, "verilog", "work")} - _build_files(platform.device, - sources, - platform.verilog_include_paths, - named_sc, - named_pc, - build_name) - if run: - _run_quartus(build_name, quartus_path) - - os.chdir("..") - - return v_output.ns - - def add_period_constraint(self, platform, clk, period): - # TODO: handle differential clk - platform.add_platform_command( - "set_global_assignment -name duty_cycle 50 -section_id {clk}", - clk=clk) - platform.add_platform_command( - "set_global_assignment -name fmax_requirement \"{freq} MHz\" " - "-section_id {clk}".format(freq=(1. / period) * 1000, - clk="{clk}"), - clk=clk) diff --git a/mibuild/fpgalink_programmer.py b/mibuild/fpgalink_programmer.py deleted file mode 100644 index c711b0ce..00000000 --- a/mibuild/fpgalink_programmer.py +++ /dev/null @@ -1,102 +0,0 @@ -import os - -from mibuild.generic_programmer import GenericProgrammer -from mibuild.xilinx.programmer import _create_xsvf - -try: - import fl -except ImportError: - import fpgalink3 as fl - -fl.flInitialise(0) - - -class FPGALink(GenericProgrammer): - """Using the fpgalink library from makestuff - - You will need fpgalink library installed from - https://github.com/makestuff/libfpgalink - """ - - needs_bitreverse = False - - def __init__(self, initial_vidpid=None, pin_cfg="D0D2D3D4", - fpgalink_vidpid="1D50:602B:0002", flash_proxy_basename=None): - """ - Parameters - ---------- - initial_vidpid : string - The USB vendor and product id of the device before fpgalink - firmware is loaded onto the device. - - Format is vid:pid as 4 digit hex numbers. - - pin_cfg : string - FPGALink pin configuration string describing how the JTAG interface - is hooked up to the programmer. - - fpgalink_vidpid : string - The USB vendor, product and device id of the device after the - fpgalink firmware is loaded onto the device. - - Format is vid:pid:did as 4 digit hex numbers. - Defaults to 1D50:602B:0002 which is the makestuff FPGALink device. - """ - GenericProgrammer.__init__(self, flash_proxy_basename) - self.initial_vidpid = initial_vidpid - self.fpgalink_vidpid = fpgalink_vidpid - self.pin_cfg = pin_cfg - - def open_device(self): - ivp = self.initial_vidpid - vp = self.fpgalink_vidpid - - print("Attempting to open connection to FPGALink device", vp, "...") - try: - handle = fl.flOpen(self.fpgalink_vidpid) - except fl.FLException as ex: - if not ivp: - raise FLException( - "Could not open FPGALink device at {0} and" - " no initial VID:PID was supplied".format(vp)) - - print("Loading firmware into %s..." % ivp) - fl.flLoadStandardFirmware(ivp, vp) - - print("Awaiting renumeration...") - if not fl.flAwaitDevice(vp, 600): - raise fl.FLException( - "FPGALink device did not renumerate properly" - " as {0}".format(vp)) - - print("Attempting to open connection to FPGALink device", vp, - "again...") - handle = fl.flOpen(vp) - - # Only Nero capable hardware support doing programming. - assert fl.flIsNeroCapable(handle) - print("Cable connection opened.") - return handle - - def load_bitstream(self, bitstream_file): - n = 27 - - xsvf_file = os.path.splitext(bitstream_file)[0]+'.xsvf' - print("\nGenerating xsvf formatted bitstream") - print("="*n) - if os.path.exists(xsvf_file): - os.unlink(xsvf_file) - _create_xsvf(bitstream_file, xsvf_file) - print("\n"+"="*n+"\n") - - print("Programming %s to device." % xsvf_file) - print("="*n) - handle = self.open_device() - print("Programming device...") - fl.flProgram(handle, "J:"+self.pin_cfg, progFile=xsvf_file) - print("Programming successful!") - print("="*n+"\n") - fl.flClose(handle) - - def flash(self, address, data_file): - raise NotImplementedError("Not supported yet.") diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py deleted file mode 100644 index 04d4b3b4..00000000 --- a/mibuild/generic_platform.py +++ /dev/null @@ -1,363 +0,0 @@ -import os -import sys - -from migen.fhdl.std import Signal -from migen.genlib.record import Record -from migen.genlib.io import CRG -from migen.fhdl import verilog, edif -from migen.util.misc import autotype - -from mibuild import tools - - -class ConstraintError(Exception): - pass - - -class Pins: - def __init__(self, *identifiers): - self.identifiers = [] - for i in identifiers: - self.identifiers += i.split() - - def __repr__(self): - return "{}('{}')".format(self.__class__.__name__, - " ".join(self.identifiers)) - - -class IOStandard: - def __init__(self, name): - self.name = name - - def __repr__(self): - return "{}('{}')".format(self.__class__.__name__, self.name) - - -class Drive: - def __init__(self, strength): - self.strength = strength - - def __repr__(self): - return "{}('{}')".format(self.__class__.__name__, self.strength) - - -class Misc: - def __init__(self, misc): - self.misc = misc - - def __repr__(self): - return "{}({})".format(self.__class__.__name__, repr(self.misc)) - - -class Subsignal: - def __init__(self, name, *constraints): - self.name = name - self.constraints = list(constraints) - - def __repr__(self): - return "{}('{}', {})".format( - self.__class__.__name__, - self.name, - ", ".join([repr(constr) for constr in self.constraints])) - - -class PlatformInfo: - def __init__(self, info): - self.info = info - - def __repr__(self): - return "{}({})".format(self.__class__.__name__, repr(self.info)) - - -def _lookup(description, name, number): - for resource in description: - if resource[0] == name and (number is None or resource[1] == number): - return resource - raise ConstraintError("Resource not found: {}:{}".format(name, number)) - - -def _resource_type(resource): - t = None - for element in resource[2:]: - if isinstance(element, Pins): - assert(t is None) - t = len(element.identifiers) - elif isinstance(element, Subsignal): - if t is None: - t = [] - - assert(isinstance(t, list)) - n_bits = None - for c in element.constraints: - if isinstance(c, Pins): - assert(n_bits is None) - n_bits = len(c.identifiers) - - t.append((element.name, n_bits)) - - return t - - -class ConnectorManager: - def __init__(self, connectors): - self.connector_table = dict() - for connector in connectors: - cit = iter(connector) - conn_name = next(cit) - if isinstance(connector[1], str): - pin_list = [] - for pins in cit: - pin_list += pins.split() - pin_list = [None if pin == "None" else pin for pin in pin_list] - elif isinstance(connector[1], dict): - pin_list = connector[1] - else: - raise ValueError("Unsupported pin list type {} for connector" - " {}".format(type(connector[1]), conn_name)) - if conn_name in self.connector_table: - raise ValueError( - "Connector specified more than once: {}".format(conn_name)) - - self.connector_table[conn_name] = pin_list - - def resolve_identifiers(self, identifiers): - r = [] - for identifier in identifiers: - if ":" in identifier: - conn, pn = identifier.split(":") - if pn.isdigit(): - pn = int(pn) - - r.append(self.connector_table[conn][pn]) - else: - r.append(identifier) - - return r - - -def _separate_pins(constraints): - pins = None - others = [] - for c in constraints: - if isinstance(c, Pins): - assert(pins is None) - pins = c.identifiers - else: - others.append(c) - - return pins, others - - -class ConstraintManager: - def __init__(self, io, connectors): - self.available = list(io) - self.matched = [] - self.platform_commands = [] - self.connector_manager = ConnectorManager(connectors) - - def add_extension(self, io): - self.available.extend(io) - - def request(self, name, number=None): - resource = _lookup(self.available, name, number) - rt = _resource_type(resource) - if isinstance(rt, int): - obj = Signal(rt, name_override=resource[0]) - else: - obj = Record(rt, name=resource[0]) - - for element in resource[2:]: - if isinstance(element, PlatformInfo): - obj.platform_info = element.info - break - - self.available.remove(resource) - self.matched.append((resource, obj)) - return obj - - def lookup_request(self, name, number=None): - for resource, obj in self.matched: - if resource[0] == name and (number is None or - resource[1] == number): - return obj - - raise ConstraintError("Resource not found: {}:{}".format(name, number)) - - def add_platform_command(self, command, **signals): - self.platform_commands.append((command, signals)) - - def get_io_signals(self): - r = set() - for resource, obj in self.matched: - if isinstance(obj, Signal): - r.add(obj) - else: - r.update(obj.flatten()) - - return r - - def get_sig_constraints(self): - r = [] - for resource, obj in self.matched: - name = resource[0] - number = resource[1] - has_subsignals = False - top_constraints = [] - for element in resource[2:]: - if isinstance(element, Subsignal): - has_subsignals = True - else: - top_constraints.append(element) - - if has_subsignals: - for element in resource[2:]: - if isinstance(element, Subsignal): - sig = getattr(obj, element.name) - pins, others = _separate_pins(top_constraints + - element.constraints) - pins = self.connector_manager.resolve_identifiers(pins) - r.append((sig, pins, others, - (name, number, element.name))) - else: - pins, others = _separate_pins(top_constraints) - pins = self.connector_manager.resolve_identifiers(pins) - r.append((obj, pins, others, (name, number, None))) - - return r - - def get_platform_commands(self): - return self.platform_commands - - -class GenericPlatform: - def __init__(self, device, io, connectors=[], name=None): - self.device = device - self.constraint_manager = ConstraintManager(io, connectors) - if name is None: - name = self.__module__.split(".")[-1] - self.name = name - self.sources = set() - self.verilog_include_paths = set() - self.finalized = False - - def request(self, *args, **kwargs): - return self.constraint_manager.request(*args, **kwargs) - - def lookup_request(self, *args, **kwargs): - return self.constraint_manager.lookup_request(*args, **kwargs) - - def add_period_constraint(self, clk, period): - raise NotImplementedError - - def add_platform_command(self, *args, **kwargs): - return self.constraint_manager.add_platform_command(*args, **kwargs) - - def add_extension(self, *args, **kwargs): - return self.constraint_manager.add_extension(*args, **kwargs) - - def finalize(self, fragment, *args, **kwargs): - if self.finalized: - raise ConstraintError("Already finalized") - # if none exists, create a default clock domain and drive it - if not fragment.clock_domains: - if not hasattr(self, "default_clk_name"): - raise NotImplementedError( - "No default clock and no clock domain defined") - crg = CRG(self.request(self.default_clk_name)) - fragment += crg.get_fragment() - - self.do_finalize(fragment, *args, **kwargs) - self.finalized = True - - def do_finalize(self, fragment, *args, **kwargs): - """overload this and e.g. add_platform_command()'s after the modules - had their say""" - if hasattr(self, "default_clk_period"): - try: - self.add_period_constraint( - self.lookup_request(self.default_clk_name), - self.default_clk_period) - except ConstraintError: - pass - - def add_source(self, filename, language=None, library=None): - if language is None: - language = tools.language_by_filename(filename) - - if language is None: - language = "verilog" # default to Verilog - - if library is None: - library = "work" # default to work - - filename = os.path.abspath(filename) - if sys.platform == "win32" or sys.platform == "cygwin": - filename = filename.replace("\\", "/") - self.sources.add((filename, language, library)) - - def add_sources(self, path, *filenames, language=None, library=None): - for f in filenames: - self.add_source(os.path.join(path, f), language, library) - - def add_source_dir(self, path, recursive=True, library=None): - dir_files = [] - if recursive: - for root, dirs, files in os.walk(path): - for filename in files: - dir_files.append(os.path.join(root, filename)) - else: - for item in os.listdir(path): - if os.path.isfile(os.path.join(path, item)): - dir_files.append(os.path.join(path, item)) - for filename in dir_files: - language = tools.language_by_filename(filename) - if language is not None: - self.add_source(filename, language, library) - - def add_verilog_include_path(self, path): - path = os.path.abspath(path) - if sys.platform == "win32" or sys.platform == "cygwin": - path = path.replace("\\", "/") - self.verilog_include_paths.add(path) - - def resolve_signals(self, vns): - # resolve signal names in constraints - sc = self.constraint_manager.get_sig_constraints() - named_sc = [(vns.get_name(sig), pins, others, resource) - for sig, pins, others, resource in sc] - # resolve signal names in platform commands - pc = self.constraint_manager.get_platform_commands() - named_pc = [] - for template, args in pc: - name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items()) - named_pc.append(template.format(**name_dict)) - - return named_sc, named_pc - - def get_verilog(self, fragment, **kwargs): - return verilog.convert( - fragment, - self.constraint_manager.get_io_signals(), - create_clock_domains=False, **kwargs) - - def get_edif(self, fragment, cell_library, vendor, device, **kwargs): - return edif.convert( - fragment, - self.constraint_manager.get_io_signals(), - cell_library, vendor, device, **kwargs) - - def build(self, fragment): - raise NotImplementedError("GenericPlatform.build must be overloaded") - - def build_cmdline(self, *args, **kwargs): - arg = sys.argv[1:] - if len(arg) % 2: - print("Missing value for option: {}".format(sys.argv[-1])) - sys.exit(1) - - argdict = dict((k, autotype(v)) for k, v in zip(*[iter(arg)] * 2)) - kwargs.update(argdict) - self.build(*args, **kwargs) - - def create_programmer(self): - raise NotImplementedError diff --git a/mibuild/generic_programmer.py b/mibuild/generic_programmer.py deleted file mode 100644 index 82a1ebe0..00000000 --- a/mibuild/generic_programmer.py +++ /dev/null @@ -1,31 +0,0 @@ -import os - - -class GenericProgrammer: - def __init__(self, flash_proxy_basename=None): - self.flash_proxy_basename = flash_proxy_basename - self.flash_proxy_dirs = [ - "~/.migen", "/usr/local/share/migen", "/usr/share/migen", - "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs"] - - def set_flash_proxy_dir(self, flash_proxy_dir): - if flash_proxy_dir is not None: - self.flash_proxy_dirs = [flash_proxy_dir] - - def find_flash_proxy(self): - for d in self.flash_proxy_dirs: - fulldir = os.path.abspath(os.path.expanduser(d)) - fullname = os.path.join(fulldir, self.flash_proxy_basename) - if os.path.exists(fullname): - return fullname - raise OSError("Failed to find flash proxy bitstream") - - # must be overloaded by specific programmer - def load_bitstream(self, bitstream_file): - raise NotImplementedError - - # must be overloaded by specific programmer - def flash(self, address, data_file): - raise NotImplementedError - - diff --git a/mibuild/lattice/__init__.py b/mibuild/lattice/__init__.py deleted file mode 100644 index 02116134..00000000 --- a/mibuild/lattice/__init__.py +++ /dev/null @@ -1,2 +0,0 @@ -from mibuild.lattice.platform import LatticePlatform -from mibuild.lattice.programmer import LatticeProgrammer diff --git a/mibuild/lattice/common.py b/mibuild/lattice/common.py deleted file mode 100644 index 090d3fc0..00000000 --- a/mibuild/lattice/common.py +++ /dev/null @@ -1,41 +0,0 @@ -from migen.fhdl.std import * -from migen.genlib.io import * - -from migen.genlib.resetsync import AsyncResetSynchronizer - - -class LatticeAsyncResetSynchronizerImpl(Module): - def __init__(self, cd, async_reset): - rst1 = Signal() - self.specials += [ - Instance("FD1S3BX", i_D=0, i_PD=async_reset, - i_CK=cd.clk, o_Q=rst1), - Instance("FD1S3BX", i_D=rst1, i_PD=async_reset, - i_CK=cd.clk, o_Q=cd.rst) - ] - - -class LatticeAsyncResetSynchronizer: - @staticmethod - def lower(dr): - return LatticeAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) - - -class LatticeDDROutputImpl(Module): - def __init__(self, i1, i2, o, clk): - self.specials += Instance("ODDRXD1", - synthesis_directive="ODDRAPPS=\"SCLK_ALIGNED\"", - i_SCLK=clk, - i_DA=i1, i_DB=i2, o_Q=o, - ) - - -class LatticeDDROutput: - @staticmethod - def lower(dr): - return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) - -lattice_special_overrides = { - AsyncResetSynchronizer: LatticeAsyncResetSynchronizer, - DDROutput: LatticeDDROutput -} diff --git a/mibuild/lattice/diamond.py b/mibuild/lattice/diamond.py deleted file mode 100644 index 0b9f486c..00000000 --- a/mibuild/lattice/diamond.py +++ /dev/null @@ -1,104 +0,0 @@ -# This file is Copyright (c) 2015 Florent Kermarrec -# License: BSD - -import os -import subprocess -import shutil - -from migen.fhdl.structure import _Fragment -from mibuild.generic_platform import * - -from mibuild import tools -from mibuild.lattice import common - - -def _format_constraint(c): - if isinstance(c, Pins): - return ("LOCATE COMP ", " SITE " + "\"" + c.identifiers[0] + "\"") - elif isinstance(c, IOStandard): - return ("IOBUF PORT ", " IO_TYPE=" + c.name) - elif isinstance(c, Misc): - return c.misc - - -def _format_lpf(signame, pin, others, resname): - fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)] - r = "" - for pre, suf in fmt_c: - r += pre + "\"" + signame + "\"" + suf + ";\n" - return r - - -def _build_lpf(named_sc, named_pc): - r = "BLOCK RESETPATHS;\n" - r += "BLOCK ASYNCPATHS;\n" - for sig, pins, others, resname in named_sc: - if len(pins) > 1: - for i, p in enumerate(pins): - r += _format_lpf(sig + "[" + str(i) + "]", p, others, resname) - else: - r += _format_lpf(sig, pins[0], others, resname) - if named_pc: - r += "\n" + "\n\n".join(named_pc) - return r - - -def _build_files(device, sources, vincpaths, build_name): - tcl = [] - tcl.append("prj_project new -name \"{}\" -impl \"implementation\" -dev {} -synthesis \"synplify\"".format(build_name, device)) - for path in vincpaths: - tcl.append("prj_impl option {include path} {\"" + path + "\"}") - for filename, language, library in sources: - tcl.append("prj_src add \"" + filename + "\" -work " + library) - tcl.append("prj_run Synthesis -impl implementation -forceOne") - tcl.append("prj_run Translate -impl implementation") - tcl.append("prj_run Map -impl implementation") - tcl.append("prj_run PAR -impl implementation") - tcl.append("prj_run Export -impl implementation -task Bitgen") - tools.write_to_file(build_name + ".tcl", "\n".join(tcl)) - - -def _run_diamond(build_name, source, ver=None): - if sys.platform == "win32" or sys.platform == "cygwin": - build_script_contents = "REM Autogenerated by mibuild\n" - build_script_contents = "pnmainc " + build_name + ".tcl\n" - build_script_file = "build_" + build_name + ".bat" - tools.write_to_file(build_script_file, build_script_contents) - r = subprocess.call([build_script_file]) - shutil.copy(os.path.join("implementation", build_name + "_implementation.bit"), build_name + ".bit") - else: - raise NotImplementedError - - if r != 0: - raise OSError("Subprocess failed") - - -class LatticeDiamondToolchain: - def build(self, platform, fragment, build_dir="build", build_name="top", - diamond_path="/opt/Diamond", run=True): - tools.mkdir_noerror(build_dir) - os.chdir(build_dir) - - if not isinstance(fragment, _Fragment): - fragment = fragment.get_fragment() - platform.finalize(fragment) - - v_output = platform.get_verilog(fragment) - named_sc, named_pc = platform.resolve_signals(v_output.ns) - v_file = build_name + ".v" - v_output.write(v_file) - sources = platform.sources | {(v_file, "verilog", "work")} - _build_files(platform.device, sources, platform.verilog_include_paths, build_name) - - tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc)) - - if run: - _run_diamond(build_name, diamond_path) - - os.chdir("..") - - return v_output.ns - - def add_period_constraint(self, platform, clk, period): - # TODO: handle differential clk - platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk) diff --git a/mibuild/lattice/platform.py b/mibuild/lattice/platform.py deleted file mode 100644 index 08be54e9..00000000 --- a/mibuild/lattice/platform.py +++ /dev/null @@ -1,26 +0,0 @@ -from mibuild.generic_platform import GenericPlatform -from mibuild.lattice import common, diamond - - -class LatticePlatform(GenericPlatform): - bitstream_ext = ".bit" - - def __init__(self, *args, toolchain="diamond", **kwargs): - GenericPlatform.__init__(self, *args, **kwargs) - if toolchain == "diamond": - self.toolchain = diamond.LatticeDiamondToolchain() - else: - raise ValueError("Unknown toolchain") - - def get_verilog(self, *args, special_overrides=dict(), **kwargs): - so = dict(common.lattice_special_overrides) - so.update(special_overrides) - return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) - - def build(self, *args, **kwargs): - return self.toolchain.build(self, *args, **kwargs) - - def add_period_constraint(self, clk, period): - if hasattr(clk, "p"): - clk = clk.p - self.toolchain.add_period_constraint(self, clk, period) diff --git a/mibuild/lattice/programmer.py b/mibuild/lattice/programmer.py deleted file mode 100644 index fc866496..00000000 --- a/mibuild/lattice/programmer.py +++ /dev/null @@ -1,53 +0,0 @@ -import os -import subprocess - -from mibuild.generic_programmer import GenericProgrammer -from mibuild import tools - -# XXX Lattice programmer need an .xcf file, will need clean up and support for more parameters -_xcf_template = """ - - - - - - JTAG - - - 1 - Lattice - LatticeECP3 - LFE3-35EA - {bitstream_file} - Fast Program - - - - SEQUENTIAL - ENTIRED CHAIN - No Override - TLR - TLR - - - - USB2 - FTUSB-0 - Dual RS232-HS A Location 0000 Serial A - - TRST ABSENT; - ISPEN ABSENT; - - - -""" - - -class LatticeProgrammer(GenericProgrammer): - needs_bitreverse = False - - def load_bitstream(self, bitstream_file): - xcf_file = bitstream_file.replace(".bit", ".xcf") - xcf_content = _xcf_template.format(bitstream_file=bitstream_file) - tools.write_to_file(xcf_file, xcf_content) - subprocess.call(["pgrcmd", "-infile", xcf_file]) diff --git a/mibuild/openocd.py b/mibuild/openocd.py deleted file mode 100644 index 47e51c7e..00000000 --- a/mibuild/openocd.py +++ /dev/null @@ -1,30 +0,0 @@ -import subprocess - -from mibuild.generic_programmer import GenericProgrammer - - -class OpenOCD(GenericProgrammer): - needs_bitreverse = False - - def __init__(self, config, flash_proxy_basename=None): - GenericProgrammer.__init__(self, flash_proxy_basename) - self.config = config - - def load_bitstream(self, bitstream): - script = "; ".join([ - "init", - "pld load 0 {}".format(bitstream), - "exit", - ]) - subprocess.call(["openocd", "-f", self.config, "-c", script]) - - def flash(self, address, data): - flash_proxy = self.find_flash_proxy() - script = "; ".join([ - "init", - "jtagspi_init 0 {}".format(flash_proxy), - "jtagspi_program {} 0x{:x}".format(data, address), - "fpga_program", - "exit" - ]) - subprocess.call(["openocd", "-f", self.config, "-c", script]) diff --git a/mibuild/platforms/__init__.py b/mibuild/platforms/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/mibuild/platforms/apf27.py b/mibuild/platforms/apf27.py deleted file mode 100644 index ee21f792..00000000 --- a/mibuild/platforms/apf27.py +++ /dev/null @@ -1,149 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_ios = [ - ("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")), - ("fpga_reset", 0, Pins("T9"), IOStandard("LVCMOS18"), Drive("8")), - ("fpga_initb", 0, Pins("T12"), IOStandard("LVCMOS18"), Drive("8")), - ("weim", 0, - Subsignal("cs4_dtack", Pins("R3"), IOStandard("LVCMOS18"), Drive("8")), - Subsignal("cs5n", Pins("P10"), IOStandard("LVCMOS18")), - Subsignal("eb0n", Pins("P9"), IOStandard("LVCMOS18")), - Subsignal("oen", Pins("R9"), IOStandard("LVCMOS18")), - Subsignal("data", - Pins("T5 T6 P7 N8 P12 T13 R13 T14 P5 N6 T3 T11 T4 R5 M10 T10"), - IOStandard("LVCMOS18"), Drive("8")), - Subsignal("addr", - Pins("N5 L7 M7 M8 L8 L9 L10 M11 P11 N11 N12 P13"), - IOStandard("LVCMOS18")) - ) -] - -_connectors = [ - ("J2", - "None", # no 0 pin - "None", # 1 +3v3 - "None", # 2 +3v3 - "None", # 3 GND - "None", # 4 GND - "None", # 5 DP USB_OTG_PHY +3V3 - "None", # 6 DM USB_OTG_PHY +3V3 - "None", # 7 VBUS USB_OTG_ PHY +3V3 - "None", # 8 PSW_N USB_OTG_PHY +3V3 - "None", # 9 ID USB_OTG_PHY +3V3 - "None", # 10 FAULT USB_OTG_PHY +3V3 - "None", # 11 RXP Ethernet_PHY +3V3 - "None", # 12 RXN Ethernet_PHY +3V3 - "None", # 13 ETH_LINK Ethernet_PHY +2V8 - "None", # 14 PC_VS2 PC +2V8 PF13 - "None", # 15 PC_VS1 PC +2V8 PF14 - "None", # 16 PC_PWRON PC +2V8 PF16 - "None", # 17 PC_READY PC +2V8 PF17 - "None", # 18 PWM0 PWM0 +2V8 PE5 - "None", # 19 TOUT GPT +2V8 PC14 - "None", # 20 GND POWER - "None", # 21 VCC01 (IN) BANK1 SUPPLY VCCO1 - "C16", # 22 IO_L24P_1 FPGA_BANK1 VCC01 - "C15", # 23 IO_L24N_1 FPGA_BANK1 VCC01 - "D16", # 24 IO_L22_P1 FPGA_BANK1 VCC01 - "None", # 25 GND POWER - "B14", # 26 IO_L02N_0 FPGA_BANK0 VCCO0 - "B15", # 27 IO_L02P_0 FPGA_BANK0 - "A13", # 28 IO_L04N_0 FPGA_BANK0 - "A14", # 29 IO_L04P_0 FPGA_BANK0 VCCO0 - "D11", # 30 IO_L03N_0 FPGA_BANK0 VCCO0 - "C12", # 31 IO_L03P_0 FPGA_BANK0 VCCO0 - "A10", # 32 IO_L08N_0 FPGA_BANK0 VCCO0 - "B10", # 33 IO_L08P_0 FPGA_BANK0 VCCO0 - "A9", # 34 IO_L10N_0 / GLCK7 FPGA_BANK0 VCCO0 - "C9", # 35 IO_L10P_0 / GCLK6 FPGA_BANK0 VCCO0 - "B8", # 36 IO_L12N_0 / GCLK11 FPGA_BANK0 VCCO0 - "A8", # 37 IO_L12P_0 / GCLK10 FPGA_BANK0 VCCO0 - "B6", # 38 IO_L15N_0 FPGA_BANK0 VCCO0 - "A6", # 39 IO_L15P_0 FPGA_BANK0 VCCO0 - "B4", # 40 IO_L18N_0 FPGA_BANK0 VCCO0 - "A4", # 41 IO_L18P_0 FPGA_BANK0 VCCO0 - "None", # 42 GND POWER - "N3", # 43 IO_L24P_3 FPGA_BANK3 VCCO3 - "R1", # 44 IO_L23P_3 FPGA_BANK3 VCCO3 - "P1", # 45 IO_L22N_3 FPGA_BANK3 VCCO3 - "N1", # 46 IO_L20N_3 FPGA_BANK3 VCCO3 - "M1", # 47 IO_L20P_3 FPGA_BANK3 VCCO3 - "H3", # 48 IO_L12P_3 FPGA_BANK3 VCCO3 - "K1", # 49 IO_L15N_3 FPGA_BANK3 VCCO3 - "J1", # 50 IO_L14N_3 FPGA_BANK3 VCCO3 - "H1", # 51 IO_L11N_3 FPGA_BANK3 VCCO3 - "G1", # 52 IO_L08N_3 FPGA_BANK3 VCCO3 - "F1", # 53 IO_L08P_3 FPGA_BANK3 VCCO3 - "E1", # 54 IO_L03N_3 FPGA_BANK3 VCCO3 - "D1", # 55 IO_LO3P_3 FPGA_BANK3 VCCO3 - "C1", # 56 IO_L01N_3 FPGA_BANK3 VCCO3 - "None", # 57 GND POWER - "None", # 58 TRSTN JTAG +2V8 - "None", # 59 TDI JTAG +2V8 - "None", # 60 TCK JTAG +2V8 - "None", # 61 TDO JTAG +2V8 - "None", # 62 TMS JTAG +2V8 - "None", # 63 GND POWER - "C2", # 64 IO_L01P_3 FPGA_BANK3 VCCO3 - "D3", # 65 IO_L02N_3 FPGA_BANK3 VCCO3 - "D4", # 66 IO_L02P_3 FPGA_BANK3 VCCO3 - "F4", # 67 IP_LO4N_3 FPGA_BANK3 VCCO3 - "G2", # 68 IO_L11P_3 FPGA_BANK3 VCCO3 - "J2", # 69 IO_L14P_3 FPGA_BANK3 VCCO3 - "K3", # 70 IO_L15P_3 FPGA_BANK3 VCCO3 - "J3", # 71 IO_L12N_3 FPGA_BANK3 VCCO3 - "N2", # 72 IO_L22P_3 FPGA_BANK3 VCCO3 - "P2", # 73 IO_L23N_3 FPGA_BANK3 VCCO3 - "M4", # 74 IO_L24N_3 FPGA_BANK3 VCCO3 - "L6", # 75 IP_L25N_3 FPGA_BANK3 VCCO3 - "None", # 76 VCCO3 (IN) BANK3 SUPPLY VCCO3 (3.3Vmax) - "None", # 77 VCCO3 (IN) BANK3 SUPPLY VCCO3 (3.3Vmax) - "A3", # 78 IO_L19P_0 FPGA_BANK0 VCCO0 - "B3", # 79 IO_L19N_0 FPGA_BANK0 VCCO0 - "A5", # 80 IO_L17P_0 FPGA_BANK0 VCCO0 - "C5", # 81 IO_L17N_0 FPGA_BANK0 VCCO0 - "D7", # 82 IO_L16P_0 FPGA_BANK0 VCCO0 - "C6", # 83 IO_L16N_0 FPGA_BANK0 VCCO0 - "C8", # 84 IO_L11P_0 / GCLK8 FPGA_BANK0 VCCO0 - "D8", # 85 IO_L11N_0 / GCLK9 FPGA_BANK0 VCCO0 - "C10", # 86 IO_L09P_0 / GCLK4 FPGA_BANK0 VCCO0 - "D9", # 87 IO_L09N_0 / GCLK5 FPGA_BANK0 VCCO0 - "C11", # 88 IO_L07P_0 FPGA_BANK0 VCCO0 - "A11", # 89 IO_L07N_0 FPGA_BANK0 VCCO0 - "D13", # 90 IO_L01P_0 FPGA_BANK0 VCCO0 - "C13", # 91 IO_L01N_0 FPGA_BANK0 VCCO0 - "None", # 92 VCCO0 (IN) BANK0 SUPPLY VCCO0 (3.3Vmax) - "None", # 93 VCCO0 (IN) BANK0 SUPPLY VCCO0 (3.3Vmax) - "None", # 94 GND POWER VCCO0 A13 - "D15", # 95 IO_L22N_1 FPGA_BANK1 VCC01 - "E13", # 96 IO_L23P_1 FPGA_BANK1 VCC01 - "D14", # 97 IO_L23N_1 FPGA_BANK1 VCC01 - "E14", # 98 IO_L20P_1 FPGA_BANK1 VCC01 - "F13", # 99 IO_L20N_1 FPGA_BANK1 VCC01 - "None", # 100 GND POWER (3.3Vmax) - "None", # 101 USR_RESETN (open CONFIG Pos PC15 +2V8 drain with pullup) - "None", # 102 TIN GPT +2V8 - "None", # 103 EXTAL_26M CONFIG +2V5 - "None", # 104 RX3 RS232_3 RS232 - "None", # 105 TX3 RS232_3 RS232 - "None", # 106 RX1 RS232_1 RS232 - "None", # 107 TX1 RS232_1 RS232 - "None", # 108 BOOT CONFIG +2V8 - "None", # 109 TXN Ethernet_PHY +3V3 - "None", # 110 TXP Ethernet_PHY +3V3 - "None", # 111 ETH_ACTIVITY Ethernet_PHY +2V8 - "None", # 112 USBH2_NXT USB_HOST2 +2V5 PA3 - "None", # 113 USBH2_DIR USB_HOST2 +2V5 PA1 - "None", # 114 USBH2_DATA7 USB_HOST2 +2V5 PA2 - "None", # 115 USBH2_STP USB_HOST2 +2V5 PA4 - "None") # 116 USBH2_CLK USB_HOST2 +2V5 PA0 -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk0" - default_clk_period = 10 - - def __init__(self): - XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors) diff --git a/mibuild/platforms/apf51.py b/mibuild/platforms/apf51.py deleted file mode 100644 index 4cfaa9d8..00000000 --- a/mibuild/platforms/apf51.py +++ /dev/null @@ -1,176 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_ios = [ - ("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")), - ("clko", 0, Pins("N7"), IOStandard("LVCMOS33")), - ("fpga_initb", 0, Pins("P3"), IOStandard("LVCMOS33")), - ("fpga_program", 0, Pins("R2"), IOStandard("LVCMOS33")), - ("eim", 0, - Subsignal("bclk", Pins("N12")), - Subsignal("eb1", Pins("P13")), - Subsignal("cs1", Pins("R11")), - Subsignal("cs2", Pins("N9")), - Subsignal("lba", Pins("R9")), - Subsignal("eb0", Pins("P7")), - Subsignal("oe", Pins("R7")), - Subsignal("rw", Pins("R6")), - Subsignal("dtack", Pins("N4")), - Subsignal("wait", Pins("R4")), - Subsignal("da", Pins("N6 L5 L6 R5 P5 N11 M11 P11 L8 K8 M8 M10 L9 R10 N5 M5")), - IOStandard("LVCMOS33") - ) -] - -_connectors = [ - ("J2", - "None", # No 0 pin - "None", # 1 FPGA Bank1 power - "None", # 2 FPGA Bank1 power - "None", # 3 GND - "B14", # 4 IO_L1P_A25_1 - "B15", # 5 IO_L1N_A24_VREF_1 - "C14", # 6 IO_L33P_A15_M1A10_1 - "C15", # 7 IO_L33N_A14_M1A4_1 - "D13", # 8 IO_L35P_A11_M1A7_1 - "D15", # 9 IO_L35N_A10_M1A2_1 - "E14", # 10 IO_L37P_A7_M1A0_1 - "E15", # 11 IO_L37N_A6_M1A1_1 - "None", # 12 GND - "F13", # 13 IO_L39P_M1A3_1 - "F15", # 14 IO_L39N_M1ODT_1 - "G14", # 15 IO_L41P_GCLK9_IRDY1_M1RASN_1 - "G15", # 16 IO_L41N_GCLK8_M1CASN_1 - "H13", # 17 IO_L42P_GCLK7_M1UDM_1 - "H15", # 18 IO_L42N_GCLK6_TRDY1_M1LDM - "J14", # 19 IO_L43P_GCLK5_M1DQ4_1 - "J15", # 20 IO_L43N_GCLK4_M1DQ5_1 - "K13", # 21 IO_L44P_A3_M1DQ6_1 - "K15", # 22 IO_L44N_A2_M1DQ7_1 - "L14", # 23 IO_L45P_A1_M1LDQS_1 - "L15", # 24 IO_L45N_A0_M1LDQSN_1 - "None", # 25 GND - "E2", # 26 IO_L52P_M3A8_3 - "E1", # 27 IO_L52N_M3A9_3 - "D3", # 28 IO_L54P_M3RESET_3 - "D1", # 29 IO_L54N_M3A11_3 - "F3", # 30 IO_L46P_M3CLK_3 - "F1", # 31 IO_L46N_M3CLKN_3 - "G2", # 32 IO_L44P_GCLK21_M3A5_3 - "G1", # 33 IO_L44N_GCLK20_M3A6_3 - "H3", # 34 IO_L42P_GCLK25_TRDY2_M3UDM_3 - "H1", # 35 IO_L42N_GCLK24_M3LDM_3 - "K3", # 36 IO_L40P_M3DQ6_3 - "K1", # 37 IO_L40N_M3DQ7_3 - "None", # 38 GND - "None", # 39 GPIO4_16 - "None", # 40 GPIO4_17 - "None", # 41 BOOT_MODE0 - "None", # 42 AUD5_RXFS - "None", # 43 AUD5_RXC - "None", # 44 GND - "None", # 45 AUD5_RXD - "None", # 46 AUD5_TXC - "None", # 47 AUD5_TXFS - "None", # 48 GND - "None", # 49 SPI2_SCLK_GPT_CMPOUT3 - "None", # 50 SPI2_MISO - "None", # 51 SPI2_MOSI - "None", # 52 SPI2_SS1 - "None", # 53 SPI2_SS2 - "None", # 54 SPI2_SS3 - "None", # 55 SPI2_RDY - "None", # 56 OWIRE - "None", # 57 GND - "None", # 58 SPI1_SCLK - "None", # 59 SPI1_MISO - "None", # 60 SPI1_MOSI - "None", # 61 SPI1_SS0 - "None", # 62 SPI1_SS1 - "None", # 63 SPI1_RDY - "None", # 64 RESET# - "None", # 65 VIO_H2 - "None", # 66 PMIC_GPIO6 - "None", # 67 TOUCH_X+ - "None", # 68 TOUCH_X- - "None", # 69 TOUCH_Y+ - "None", # 70 TOUCH_Y- - "None", # 71 AUXADCIN4 - "None", # 72 AUXADCIN3 - "None", # 73 AUXADCIN2 - "None", # 74 AUXADCIN1 - "None", # 75 PMIC_GPIO7 - "None", # 76 +1v8 - "None", # 77 RESERVED - "None", # 78 UART3_TXD - "None", # 79 UART_3_RXD - "None", # 80 UART2_TXD - "None", # 81 UART2_RXD - "None", # 82 UART2_RTS_KEY_COL7 - "None", # 83 UART2_CTS_KEY_COL6 - "None", # 84 UART1_TXD - "None", # 85 UART1_RXD - "None", # 86 UART1_RTS - "None", # 87 UART1_CTS - "None", # 88 GND - "None", # 89 AUD3_TXD - "None", # 90 AUD3_RXD - "None", # 91 AUD3_FS - "None", # 92 AUD3_CK - "None", # 93 GND - "None", # 94 AUD6_TXFS_KEY_ROW7 - "None", # 95 AUD6_TXC_KEY_ROW6 - "None", # 96 AUD6_RXD_KEY_ROW5 - "None", # 97 AUD6_TXD_KEY_ROW4 - "None", # 98 I2C2_SDA_UART3_CTS - "None", # 99 I2C2_SCL_UART3_RTS - "None", # 100 BOOT_MODE1 - "None", # 101 PWM2 - "None", # 102 PWM1 - "None", # 103 GND - "L1", # 104 IO_L39N_M3LDQSN_3 - "L2", # 105 IO_L39P_M3LDQS_3 - "J1", # 106 IO_L41N_GCLK26_M3DQ5_3 - "J2", # 107 IO_L41P_GCLK27_M3DQ4_3 - "J3", # 108 IO_L43N_GCLK22_IRDY2_M3CASN_3 - "K4", # 109 IO_L43P_GCLK23_M3RASN_3 - "J4", # 110 IO_L45N_M3ODT_3 - "K5", # 111 IO_L45P_M3A3_3 - "C1", # 112 IO_L83N_VREF_3 - "C2", # 113 IO_L83P_3 - "E3", # 114 IO_L53N_M3A12_3 - "D4", # 115 IO_L53P_M3CKE_3 - "None", # 116 GND - "P15", # 117 IO_L74N_DOUT_BUSY_1 - "P14", # 118 IO_L74P_AWAKE_1 - "N15", # 119 IO_L47N_LDC_M1DQ1_1 - "N14", # 120 IO_L47P_FWE_B_M1DQ0_1 - "M15", # 121 IO_L46N_FOE_B_M1DQ3_1 - "M13", # 122 IO_L46P_FCS_B_M1DQS2_1 - "L12", # 123 IO_L40N_GCLK10_M1A6_1 - "K12", # 124 IO_L40P_GCLK11_M1A5_1 - "K11", # 125 IO_L38N_A4_M1CLKN_1 - "K10", # 126 IO_L38P_A5_M1CLK_1 - "J13", # 127 IO_L36N_A8_M1BA1_1 - "J11", # 128 IO_L36P_A9_M1BA0_1 - "None", # 129 GND - "G13", # 130 IO_L34N_A12_M1BA2_1_NOTLX4 - "H12", # 131 IO_L34P_A13_M1WE_1_NOTLX4 - "H11", # 132 IO_L32N_A16_M1A9_1_NOTLX4 - "H10", # 133 IO_L32P_A17_M1A8_1_NOTLX4 - "F12", # 134 IO_L31N_A18_M1A12_1_NOTLX4 - "F11", # 135 IO_L31P_A19_M1CKE_1_NOTLX4 - "G12", # 136 IO_L30N_A20_M1A11_1_NOTLX4 - "G11", # 137 IO_L30P_A21_M1RESET_1_NOTLX4 - "None", # 138 GND - "None", # 139 FPGA_BANK3_POWER - "None") # 140 FPGA_BANK3_POWER -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk3" - default_clk_period = 10.526 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors) diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py deleted file mode 100644 index 7e6d47b2..00000000 --- a/mibuild/platforms/de0nano.py +++ /dev/null @@ -1,102 +0,0 @@ -# This file is Copyright (c) 2013 Florent Kermarrec -# License: BSD - -from mibuild.generic_platform import * -from mibuild.altera import AlteraPlatform -from mibuild.altera.programmer import USBBlaster - -_io = [ - ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), - - ("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")), - ("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")), - ("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")), - ("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")), - ("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")), - ("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")), - ("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")), - ("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")), - - ("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")), - ("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")), - - ("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")), - ("sw", 1, Pins("T9"), IOStandard("3.3-V LVTTL")), - ("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")), - ("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")), - - ("serial", 0, - Subsignal("tx", Pins("D3"), IOStandard("3.3-V LVTTL")), - Subsignal("rx", Pins("C3"), IOStandard("3.3-V LVTTL")) - ), - - ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")), - ("sdram", 0, - Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")), - Subsignal("ba", Pins("M7 M6")), - Subsignal("cs_n", Pins("P6")), - Subsignal("cke", Pins("L7")), - Subsignal("ras_n", Pins("L2")), - Subsignal("cas_n", Pins("L1")), - Subsignal("we_n", Pins("C2")), - Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")), - Subsignal("dm", Pins("R6 T5")), - IOStandard("3.3-V LVTTL") - ), - - ("epcs", 0, - Subsignal("data0", Pins("H2")), - Subsignal("dclk", Pins("H1")), - Subsignal("ncs0", Pins("D2")), - Subsignal("asd0", Pins("C1")), - IOStandard("3.3-V LVTTL") - ), - - ("i2c", 0, - Subsignal("sclk", Pins("F2")), - Subsignal("sdat", Pins("F1")), - IOStandard("3.3-V LVTTL") - ), - - ("g_sensor", 0, - Subsignal("cs_n", Pins("G5")), - Subsignal("int", Pins("M2")), - IOStandard("3.3-V LVTTL") - ), - - ("adc", 0, - Subsignal("cs_n", Pins("A10")), - Subsignal("saddr", Pins("B10")), - Subsignal("sclk", Pins("B14")), - Subsignal("sdat", Pins("A9")), - IOStandard("3.3-V LVTTL") - ), - - ("gpio_0", 0, - Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6", - "C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11", - "D12 B12"), - IOStandard("3.3-V LVTTL") - ), - ("gpio_1", 0, - Pins("F13 T15 T14 T13 R13 T12 R12 T11 T10 R11 P11 R10 N12 P9 N9 N11", - "L16 K16 R16 L15 P15 P16 R14 N16 N15 P14 L14 N14 M10 L13 J16 K15", - "J13 J14"), - IOStandard("3.3-V LVTTL") - ), - ("gpio_2", 0, - Pins("A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15"), - IOStandard("3.3-V LVTTL") - ), -] - - -class Platform(AlteraPlatform): - default_clk_name = "clk50" - default_clk_period = 20 - - def __init__(self): - AlteraPlatform.__init__(self, "EP4CE22F17C6", _io) - - def create_programmer(self): - return USBBlaster() diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py deleted file mode 100644 index bc67d2be..00000000 --- a/mibuild/platforms/kc705.py +++ /dev/null @@ -1,457 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT -from mibuild.xilinx.ise import XilinxISEToolchain - -_io = [ - ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), - ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), - ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), - ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")), - ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")), - ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")), - ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), - ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), - - ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), - - ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")), - ("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")), - ("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")), - ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")), - ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")), - - ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")), - ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")), - ("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")), - ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")), - - ("user_sma_clock", 0, - Subsignal("p", Pins("L25"), IOStandard("LVDS_25")), - Subsignal("n", Pins("K25"), IOStandard("LVDS_25")) - ), - ("user_sma_clock_p", 0, Pins("L25"), IOStandard("LVCMOS25")), - ("user_sma_clock_n", 0, Pins("K25"), IOStandard("LVCMOS25")), - - ("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS33")), - ("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS33")), - - ("clk200", 0, - Subsignal("p", Pins("AD12"), IOStandard("LVDS")), - Subsignal("n", Pins("AD11"), IOStandard("LVDS")) - ), - - ("clk156", 0, - Subsignal("p", Pins("K28"), IOStandard("LVDS_25")), - Subsignal("n", Pins("K29"), IOStandard("LVDS_25")) - ), - - ("i2c", 0, - Subsignal("scl", Pins("K21")), - Subsignal("sda", Pins("L21")), - IOStandard("LVCMOS25")), - - ("serial", 0, - Subsignal("cts", Pins("L27")), - Subsignal("rts", Pins("K23")), - Subsignal("tx", Pins("K24")), - Subsignal("rx", Pins("M19")), - IOStandard("LVCMOS25")), - - ("spiflash", 0, # clock needs to be accessed through STARTUPE2 - Subsignal("cs_n", Pins("U19")), - Subsignal("dq", Pins("P24", "R25", "R20", "R21")), - IOStandard("LVCMOS25") - ), - - ("mmc", 0, - Subsignal("wp", Pins("Y21")), - Subsignal("det", Pins("AA21")), - Subsignal("cmd", Pins("AB22")), - Subsignal("clk", Pins("AB23")), - Subsignal("dat", Pins("AC20 AA23 AA22 AC21")), - IOStandard("LVCMOS25")), - - ("lcd", 0, - Subsignal("db", Pins("AA13 AA10 AA11 Y10")), - Subsignal("e", Pins("AB10")), - Subsignal("rs", Pins("Y11")), - Subsignal("rw", Pins("AB13")), - IOStandard("LVCMOS15")), - - ("rotary", 0, - Subsignal("a", Pins("Y26")), - Subsignal("b", Pins("Y25")), - Subsignal("push", Pins("AA26")), - IOStandard("LVCMOS25")), - - ("hdmi", 0, - Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")), - Subsignal("de", Pins("H17")), - Subsignal("clk", Pins("K18")), - Subsignal("vsync", Pins("H20")), - Subsignal("hsync", Pins("J18")), - Subsignal("int", Pins("AH24")), - Subsignal("spdif", Pins("J17")), - Subsignal("spdif_out", Pins("G20")), - IOStandard("LVCMOS25")), - - ("ddram", 0, - Subsignal("a", Pins( - "AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14", - "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"), - IOStandard("SSTL15")), - Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")), - Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), - IOStandard("SSTL15")), - Subsignal("dq", Pins( - "AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15", - "AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18", - "AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19", - "AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15", - "AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6", - "AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1", - "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", - "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), - IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), - IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), - IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")), - Misc("SLEW=FAST"), - Misc("VCCAUX_IO=HIGH") - ), - - ("eth_clocks", 0, - Subsignal("tx", Pins("M28")), - Subsignal("gtx", Pins("K30")), - Subsignal("rx", Pins("U27")), - IOStandard("LVCMOS25") - ), - ("eth", 0, - Subsignal("rst_n", Pins("L20")), - Subsignal("int_n", Pins("N30")), - Subsignal("mdio", Pins("J21")), - Subsignal("mdc", Pins("R23")), - Subsignal("dv", Pins("R28")), - Subsignal("rx_er", Pins("V26")), - Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")), - Subsignal("tx_en", Pins("M27")), - Subsignal("tx_er", Pins("N29")), - Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), - IOStandard("LVCMOS25") - ), - - ("pcie_x1", 0, - Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), - Subsignal("clk_p", Pins("U8")), - Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6")), - Subsignal("rx_n", Pins("M5")), - Subsignal("tx_p", Pins("L4")), - Subsignal("tx_n", Pins("L3")) - ), - ("pcie_x2", 0, - Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), - Subsignal("clk_p", Pins("U8")), - Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6 P6")), - Subsignal("rx_n", Pins("M5 P5")), - Subsignal("tx_p", Pins("L4 M2")), - Subsignal("tx_n", Pins("L3 M1")) - ), - ("pcie_x4", 0, - Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), - Subsignal("clk_p", Pins("U8")), - Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6 P6 R4 T6")), - Subsignal("rx_n", Pins("M5 P5 R3 T5")), - Subsignal("tx_p", Pins("L4 M2 N4 P2")), - Subsignal("tx_n", Pins("L3 M1 N3 P1")) - ), - ("pcie_x8", 0, - Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), - Subsignal("clk_p", Pins("U8")), - Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")), - Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")), - Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")), - Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1")) - ) -] - -_connectors = [ - ("HPC", { - "DP1_M2C_P": "D6", - "DP1_M2C_N": "D5", - "DP2_M2C_P": "B6", - "DP2_M2C_N": "B5", - "DP3_M2C_P": "A8", - "DP3_M2C_N": "A7", - "DP1_C2M_P": "C4", - "DP1_C2M_N": "C3", - "DP2_C2M_P": "B2", - "DP2_C2M_N": "B1", - "DP3_C2M_P": "A4", - "DP3_C2M_N": "A3", - "DP0_C2M_P": "D2", - "DP0_C2M_N": "D1", - "DP0_M2C_P": "E4", - "DP0_M2C_N": "E3", - "LA06_P": "H30", - "LA06_N": "G30", - "LA10_P": "D29", - "LA10_N": "C30", - "LA14_P": "B28", - "LA14_N": "A28", - "LA18_CC_P": "F21", - "LA18_CC_N": "E21", - "LA27_P": "C19", - "LA27_N": "B19", - "HA01_CC_P": "H14", - "HA01_CC_N": "G14", - "HA05_P": "F15", - "HA05_N": "E16", - "HA09_P": "F12", - "HA09_N": "E13", - "HA13_P": "L16", - "HA13_N": "K16", - "HA16_P": "L15", - "HA16_N": "K15", - "HA20_P": "K13", - "HA20_N": "J13", - "CLK1_M2C_P": "D17", - "CLK1_M2C_N": "D18", - "LA00_CC_P": "C25", - "LA00_CC_N": "B25", - "LA03_P": "H26", - "LA03_N": "H27", - "LA08_P": "E29", - "LA08_N": "E30", - "LA12_P": "C29", - "LA12_N": "B29", - "LA16_P": "B27", - "LA16_N": "A27", - "LA20_P": "E19", - "LA20_N": "D19", - "LA22_P": "C20", - "LA22_N": "B20", - "LA25_P": "G17", - "LA25_N": "F17", - "LA29_P": "C17", - "LA29_N": "B17", - "LA31_P": "G22", - "LA31_N": "F22", - "LA33_P": "H21", - "LA33_N": "H22", - "HA03_P": "C12", - "HA03_N": "B12", - "HA07_P": "B14", - "HA07_N": "A15", - "HA11_P": "B13", - "HA11_N": "A13", - "HA14_P": "J16", - "HA14_N": "H16", - "HA18_P": "K14", - "HA18_N": "J14", - "HA22_P": "L11", - "HA22_N": "K11", - "GBTCLK1_M2C_P": "E8", - "GBTCLK1_M2C_N": "E7", - "GBTCLK0_M2C_P": "C8", - "GBTCLK0_M2C_N": "C7", - "LA01_CC_P": "D26", - "LA01_CC_N": "C26", - "LA05_P": "G29", - "LA05_N": "F30", - "LA09_P": "B30", - "LA09_N": "A30", - "LA13_P": "A25", - "LA13_N": "A26", - "LA17_CC_P": "F20", - "LA17_CC_N": "E20", - "LA23_P": "B22", - "LA23_N": "A22", - "LA26_P": "B18", - "LA26_N": "A18", - "PG_M2C": "J29", - "HA00_CC_P": "D12", - "HA00_CC_N": "D13", - "HA04_P": "F11", - "HA04_N": "E11", - "HA08_P": "E14", - "HA08_N": "E15", - "HA12_P": "C15", - "HA12_N": "B15", - "HA15_P": "H15", - "HA15_N": "G15", - "HA19_P": "H11", - "HA19_N": "H12", - "PRSNT_M2C_B": "M20", - "CLK0_M2C_P": "D27", - "CLK0_M2C_N": "C27", - "LA02_P": "H24", - "LA02_N": "H25", - "LA04_P": "G28", - "LA04_N": "F28", - "LA07_P": "E28", - "LA07_N": "D28", - "LA11_P": "G27", - "LA11_N": "F27", - "LA15_P": "C24", - "LA15_N": "B24", - "LA19_P": "G18", - "LA19_N": "F18", - "LA21_P": "A20", - "LA21_N": "A21", - "LA24_P": "A16", - "LA24_N": "A17", - "LA28_P": "D16", - "LA28_N": "C16", - "LA30_P": "D22", - "LA30_N": "C22", - "LA32_P": "D21", - "LA32_N": "C21", - "HA02_P": "D11", - "HA02_N": "C11", - "HA06_P": "D14", - "HA06_N": "C14", - "HA10_P": "A11", - "HA10_N": "A12", - "HA17_CC_P": "G13", - "HA17_CC_N": "F13", - "HA21_P": "J11", - "HA21_N": "J12", - "HA23_P": "L12", - "HA23_N": "L13", - } - ), - ("LPC", { - "GBTCLK0_M2C_P": "N8", - "GBTCLK0_M2C_N": "N7", - "LA01_CC_P": "AE23", - "LA01_CC_N": "AF23", - "LA05_P": "AG22", - "LA05_N": "AH22", - "LA09_P": "AK23", - "LA09_N": "AK24", - "LA13_P": "AB24", - "LA13_N": "AC25", - "LA17_CC_P": "AB27", - "LA17_CC_N": "AC27", - "LA23_P": "AH26", - "LA23_N": "AH27", - "LA26_P": "AK29", - "LA26_N": "AK30", - "CLK0_M2C_P": "AF22", - "CLK0_M2C_N": "AG23", - "LA02_P": "AF20", - "LA02_N": "AF21", - "LA04_P": "AH21", - "LA04_N": "AJ21", - "LA07_P": "AG25", - "LA07_N": "AH25", - "LA11_P": "AE25", - "LA11_N": "AF25", - "LA15_P": "AC24", - "LA15_N": "AD24", - "LA19_P": "AJ26", - "LA19_N": "AK26", - "LA21_P": "AG27", - "LA21_N": "AG28", - "LA24_P": "AG30", - "LA24_N": "AH30", - "LA28_P": "AE30", - "LA28_N": "AF30", - "LA30_P": "AB29", - "LA30_N": "AB30", - "LA32_P": "Y30", - "LA32_N": "AA30", - "LA06_P": "AK20", - "LA06_N": "AK21", - "LA10_P": "AJ24", - "LA10_N": "AK25", - "LA14_P": "AD21", - "LA14_N": "AE21", - "LA18_CC_P": "AD27", - "LA18_CC_N": "AD28", - "LA27_P": "AJ28", - "LA27_N": "AJ29", - "CLK1_M2C_P": "AG29", - "CLK1_M2C_N": "AH29", - "LA00_CC_P": "AD23", - "LA00_CC_N": "AE24", - "LA03_P": "AG20", - "LA03_N": "AH20", - "LA08_P": "AJ22", - "LA08_N": "AJ23", - "LA12_P": "AA20", - "LA12_N": "AB20", - "LA16_P": "AC22", - "LA16_N": "AD22", - "LA20_P": "AF26", - "LA20_N": "AF27", - "LA22_P": "AJ27", - "LA22_N": "AK28", - "LA25_P": "AC26", - "LA25_N": "AD26", - "LA29_P": "AE28", - "LA29_N": "AF28", - "LA31_P": "AD29", - "LA31_N": "AE29", - "LA33_P": "AC29", - "LA33_N": "AC30", - } - ) -] - - -class Platform(XilinxPlatform): - identifier = 0x4B37 - default_clk_name = "clk156" - default_clk_period = 6.4 - - def __init__(self, toolchain="vivado", programmer="xc3sprog"): - XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, - toolchain=toolchain) - if toolchain == "ise": - self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" - elif toolchain == "vivado": - self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] - self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] - self.programmer = programmer - - def create_programmer(self): - if self.programmer == "xc3sprog": - return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit") - elif self.programmer == "vivado": - return VivadoProgrammer() - elif self.programmer == "impact": - return iMPACT() - else: - raise ValueError("{} programmer is not supported".format(programmer)) - - def do_finalize(self, fragment): - XilinxPlatform.do_finalize(self, fragment) - try: - self.add_period_constraint(self.lookup_request("clk200").p, 5.0) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) - except ConstraintError: - pass - if isinstance(self.toolchain, XilinxISEToolchain): - self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";") - else: - self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]") diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py deleted file mode 100644 index ea0cb415..00000000 --- a/mibuild/platforms/lx9_microboard.py +++ /dev/null @@ -1,130 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_io = [ - ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"), - Misc("PULLDOWN"), Misc("TIG")), - - ("user_led", 0, Pins("P4"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), - ("user_led", 1, Pins("L6"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), - ("user_led", 2, Pins("F5"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), - ("user_led", 3, Pins("C2"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), - - ("user_dip", 0, Pins("B3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), - ("user_dip", 1, Pins("A3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), - ("user_dip", 2, Pins("B4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), - ("user_dip", 3, Pins("A4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), - - # TI CDCE913 programmable triple-output PLL - ("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz - ("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz - ("clk_y3", 0, Pins("C10"), IOStandard("LVCMOS33")), # default: 100 MHz - - # Maxim DS1088LU oscillator, not populated - ("clk_backup", 0, Pins("R8"), IOStandard("LVCMOS33")), - - # TI CDCE913 PLL I2C control - ("pll", 0, - Subsignal("scl", Pins("P12")), - Subsignal("sda", Pins("U13")), - Misc("PULLUP"), - IOStandard("LVCMOS33")), - - # Micron N25Q128 SPI Flash - ("spiflash", 0, - Subsignal("clk", Pins("R15")), - Subsignal("cs_n", Pins("V3")), - Subsignal("dq", Pins("T13 R13 T14 V14")), - IOStandard("LVCMOS33")), - - # PMOD extension connectors - ("pmod", 0, - Subsignal("d", Pins("F15 F16 C17 C18 F14 G14 D17 D18")), - IOStandard("LVCMOS33")), - ("pmod", 1, - Subsignal("d", Pins("H12 G13 E16 E18 K12 K13 F17 F18")), - IOStandard("LVCMOS33")), - - ("pmod_diff", 0, - Subsignal("io", Pins("F15 C17 F14 D17 H12 E16 K12 F17")), - Subsignal("iob", Pins("F16 C18 G14 D18 G13 E18 K13 F18")), - IOStandard("LVCMOS33")), - - ("serial", 0, - Subsignal("tx", Pins("T7"), Misc("SLEW=SLOW")), - Subsignal("rx", Pins("R7"), Misc("PULLUP")), - IOStandard("LVCMOS33")), - - ("ddram_clock", 0, - Subsignal("p", Pins("G3")), - Subsignal("n", Pins("G1")), - IOStandard("MOBILE_DDR")), # actually DIFF_ - - # Micron MT46H32M16LFBF-5 LPDDR - ("ddram", 0, - Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 " - "D2 D1 F4 D3 G6")), - Subsignal("ba", Pins("F2 F1")), - Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 " - "M3 M1 N2 N1 T2 T1 U2 U1")), - Subsignal("cke", Pins("H7")), - Subsignal("we_n", Pins("E3")), - Subsignal("cs_n", Pins("K6")), # NC! - Subsignal("cas_n", Pins("K5")), - Subsignal("ras_n", Pins("L5")), - Subsignal("dm", Pins("K3", "K4")), - Subsignal("dqs", Pins("L4", "P2")), - Subsignal("rzq", Pins("N4")), - IOStandard("MOBILE_DDR")), - - # Nat Semi DP83848J 10/100 Ethernet PHY - # pull-ups on col and rx_data set phy addr to 11111b - # and prevent isolate mode (addr 00000b) - ("eth_clocks", 0, - Subsignal("rx", Pins("L15")), - Subsignal("tx", Pins("H17")), - IOStandard("LVCMOS33")), - - ("eth", 0, - Subsignal("col", Pins("M18"), Misc("PULLUP")), - Subsignal("crs", Pins("N17"), Misc("PULLDOWN")), - Subsignal("mdc", Pins("M16"), Misc("PULLDOWN")), - Subsignal("mdio", Pins("L18"), Misc("PULLUP")), # 1k5 ext PULLUP - Subsignal("rst_n", Pins("T18"), Misc("TIG")), - Subsignal("rx_data", Pins("T17 N16 N15 P18"), Misc("PULLUP")), - Subsignal("dv", Pins("P17"), Misc("PULLDOWN")), # MII - Subsignal("rx_er", Pins("N18"), Misc("PULLUP")), # auto MDIX - Subsignal("tx_data", Pins("K18 K17 J18 J16")), - Subsignal("tx_en", Pins("L17")), - Subsignal("tx_er", Pins("L16")), # NC! - IOStandard("LVCMOS33")), - ] - - -class Platform(XilinxPlatform): - default_clk_name = "clk_y3" - default_clk_period = 10 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io) - self.add_platform_command(""" -CONFIG VCCAUX = "3.3"; -""") - self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4" - self.toolchain.ise_commands = """ -promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit -""" - - def do_finalize(self, fragment): - XilinxPlatform.do_finalize(self, fragment) - - try: - eth_clocks = self.lookup_request("eth_clocks") - self.add_period_constraint(eth_clocks.rx, 40) - self.add_period_constraint(eth_clocks.tx, 40) - self.add_platform_command(""" -TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; -TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; -""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) - except ConstraintError: - pass diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py deleted file mode 100644 index 01b9e866..00000000 --- a/mibuild/platforms/m1.py +++ /dev/null @@ -1,151 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform -from mibuild.xilinx.programmer import UrJTAG - -_io = [ - ("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), - ("user_led", 1, Pins("A16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), - - ("user_btn", 0, Pins("AB4"), IOStandard("LVCMOS33")), - ("user_btn", 1, Pins("AA4"), IOStandard("LVCMOS33")), - ("user_btn", 2, Pins("AB5"), IOStandard("LVCMOS33")), - - ("clk50", 0, Pins("AB11"), IOStandard("LVCMOS33")), - - # When executing softcore code in-place from the flash, we want - # the flash reset to be released before the system reset. - ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), - ("norflash", 0, - Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22", - "F21 K17 J17 E22 E20 H18 H19 F20", - "G19 C22 C20 D22 D21 F19 F18 D20 D19")), - Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7", - "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")), - Subsignal("oe_n", Pins("M22")), - Subsignal("we_n", Pins("N20")), - Subsignal("ce_n", Pins("M21")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8) - ), - - ("serial", 0, - Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), - Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")) - ), - - ("ddram_clock", 0, - Subsignal("p", Pins("M3")), - Subsignal("n", Pins("L4")), - IOStandard("SSTL2_I") - ), - ("ddram", 0, - Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")), - Subsignal("ba", Pins("A2 E6")), - Subsignal("cs_n", Pins("F7")), - Subsignal("cke", Pins("G7")), - Subsignal("ras_n", Pins("E5")), - Subsignal("cas_n", Pins("C4")), - Subsignal("we_n", Pins("D3")), - Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3", - "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4", - "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")), - Subsignal("dm", Pins("E1 E3 F3 G4")), - Subsignal("dqs", Pins("F1 F2 H5 H6")), - IOStandard("SSTL2_I") - ), - - ("eth_clocks", 0, - Subsignal("phy", Pins("M20")), - Subsignal("rx", Pins("H22")), - Subsignal("tx", Pins("H21")), - IOStandard("LVCMOS33") - ), - ("eth", 0, - Subsignal("rst_n", Pins("R22")), - Subsignal("dv", Pins("V21")), - Subsignal("rx_er", Pins("V22")), - Subsignal("rx_data", Pins("U22 U20 T22 T21")), - Subsignal("tx_en", Pins("N19")), - Subsignal("tx_er", Pins("M19")), - Subsignal("tx_data", Pins("M16 L15 P19 P20")), - Subsignal("col", Pins("W20")), - Subsignal("crs", Pins("W22")), - IOStandard("LVCMOS33") - ), - - ("vga_out", 0, - Subsignal("clk", Pins("A11")), - Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), - Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), - Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")), - Subsignal("hsync_n", Pins("A14")), - Subsignal("vsync_n", Pins("C15")), - Subsignal("psave_n", Pins("B14")), - IOStandard("LVCMOS33") - ), - - ("mmc", 0, - Subsignal("clk", Pins("A10")), - Subsignal("cmd", Pins("B18")), - Subsignal("dat", Pins("A18 E16 C17 A17")), - IOStandard("LVCMOS33") - ), - - # Digital video mixer extension board - ("dvi_in", 0, - Subsignal("clk", Pins("A20")), - Subsignal("data0_n", Pins("A21")), - Subsignal("data1", Pins("B21")), - Subsignal("data2_n", Pins("B22")), - Subsignal("scl", Pins("G16")), - Subsignal("sda", Pins("G17")), - IOStandard("LVCMOS33") - ), - ("dvi_in", 1, - Subsignal("clk", Pins("H17")), - Subsignal("data0_n", Pins("H16")), - Subsignal("data1", Pins("F17")), - Subsignal("data2_n", Pins("F16")), - Subsignal("scl", Pins("J16")), - Subsignal("sda", Pins("K16")), - IOStandard("LVCMOS33") - ), - ("dvi_pots", 0, - Subsignal("charge", Pins("A18")), # SD_DAT0 - Subsignal("blackout", Pins("C17")), # SD_DAT2 - Subsignal("crossfade", Pins("A17")), # SD_DAT3 - IOStandard("LVCMOS33") - ) -] - - -class Platform(XilinxPlatform): - identifier = 0x4D31 - default_clk_name = "clk50" - default_clk_period = 20 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io) - - def create_programmer(self): - return UrJTAG(cable="milkymist", flash_proxy_basename="fjmem-m1.bit") - - def do_finalize(self, fragment): - XilinxPlatform.do_finalize(self, fragment) - - try: - eth_clocks = self.lookup_request("eth_clocks") - self.add_period_constraint(eth_clocks.rx, 40) - self.add_period_constraint(eth_clocks.tx, 40) - self.add_platform_command(""" -TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; -TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; -""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) - except ConstraintError: - pass - - for i in range(2): - si = "dviclk"+str(i) - try: - self.add_period_constraint(self.lookup_request("dvi_in", i).clk, 26.7) - except ConstraintError: - pass diff --git a/mibuild/platforms/mercury.py b/mibuild/platforms/mercury.py deleted file mode 100644 index 77a884ba..00000000 --- a/mibuild/platforms/mercury.py +++ /dev/null @@ -1,138 +0,0 @@ -# This file is Copyright (c) 2015 William D. Jones -# License: BSD - -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform -from mibuild.xilinx.programmer import XC3SProg - - -_io = [ - ("clk50", 0, Pins("P43"), IOStandard("LVCMOS33")), - - ("user_btn", 0, Pins("P41"), IOStandard("LVTTL")), - - # The serial interface and flash memory have a shared SPI bus. - # FPGA is secondary - ("spiserial", 0, - Subsignal("cs_n", Pins("P39"), IOStandard("LVTTL")), - Subsignal("clk", Pins("P53"), IOStandard("LVTTL")), - Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")), - Subsignal("miso", Pins("P51"), IOStandard("LVTTL")) - ), - - # FPGA is primary - ("spiflash", 0, - Subsignal("cs_n", Pins("P27"), IOStandard("LVTTL")), - Subsignal("clk", Pins("P53"), IOStandard("LVTTL")), - Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")), - Subsignal("miso", Pins("P51"), IOStandard("LVTTL")) - ), - - ("spiflash2x", 0, - Subsignal("cs_n", Pins("P27")), - Subsignal("clk", Pins("P53")), - Subsignal("dq", Pins("P46", "P51")), - IOStandard("LVTTL"), Misc("SLEW=FAST") - ), - - # ADC over SPI- FPGA is primary - ("adc", 0, - Subsignal("cs_n", Pins("P12"), IOStandard("LVTTL")), - Subsignal("clk", Pins("P9"), IOStandard("LVTTL")), - Subsignal("mosi", Pins("P10"), IOStandard("LVTTL")), - Subsignal("miso", Pins("P21"), IOStandard("LVTTL")) - ), - - # GPIO control- SRAM and connectors are shared: these pins control how - # to access each. Recommended to combine with gpio_sram_bus extension, - # since these pins are related but not exposed on connectors. - ("gpio_ctl", 0, - Subsignal("ce_n", Pins("P3")), # Memory chip-enable. Called MEM_CEN - # in schematic. - Subsignal("bussw_oe_n", Pins("P30")), # 5V tolerant GPIO is shared - # w/ memory using this pin. - IOStandard("LVTTL"), Misc("SLEW=FAST") - ) -] - -# Perhaps define some connectors as having a specific purpose- i.e. a 5V GPIO -# bus with data, peripheral-select, and control signals? -_connectors = [ - ("GPIO", """P59 P60 P61 P62 P64 P57 - P56 P52 P50 P49 P85 P84 - P83 P78 P77 P65 P70 P71 - P72 P73 P5 P4 P6 P98 - P94 P93 P90 P89 P88 P86"""), # 5V I/O- LVTTL - ("DIO", "P20 P32 P33 P34 P35 P36 P37"), # Fast 3.3V IO (Directly attached - # to FPGA)- LVCMOS33 - ("CLKIO", "P40 P44"), # Clock IO (Can be used as GPIO)- LVCMOS33 - ("INPUT", "P68 P97 P7 P82"), # Input-only pins- LVCMOS33 - ("LED", "P13 P15 P16 P19") # LEDs can be used as pins as well- LVTTL. -] - -# Some default useful extensions- use platform.add_extension() to use, e.g. -# from mibuild.platforms import mercury -# plat = mercury.Platform() -# plat.add_extension(mercury.gpio_sram) - -# SRAM and 5V-tolerant I/O share a parallel bus on 200k gate version. The SRAM -# controller needs to take care of switching the bus between the two. Meant to -# be Cat() into one GPIO bus, and combined with gpio_ctl. -gpio_sram = [ - ("gpio_sram_bus", 0, - Subsignal("a", Pins("""GPIO:0 GPIO:1 GPIO:2 GPIO:3 - GPIO:4 GPIO:5 GPIO:6 GPIO:7 - GPIO:8 GPIO:9 GPIO:10 GPIO:11 - GPIO:12 GPIO:13 GPIO:14 GPIO:15 - GPIO:16 GPIO:17 GPIO:18 GPIO:19""")), - # A19 is actually unused- free for GPIO - # 8-bit data bus - Subsignal("d", Pins("""GPIO:20 GPIO:21 GPIO:22 GPIO:23 - GPIO:24 GPIO:25 GPIO:26 GPIO:27""")), - Subsignal("we_n", Pins("GPIO:28")), - Subsignal("unused", Pins("GPIO:29")), # Only used by GPIO. - # Subsignal("oe_n", Pins()), # If OE wasn't tied to ground on Mercury, - # this pin would be here. - IOStandard("LVTTL"), Misc("SLEW=FAST") - ) -] - -# The "serial port" is in fact over SPI. The creators of the board provide a -# VHDL file for talking over this interface. In light of space constraints and -# the fact that both the FT245RL and FPGA can BOTH be SPI primaries, however, -# it may be necessary to sacrifice two "high-speed" (DIO, INPUT) pins instead. -serial = [ - ("serial", 0, - Subsignal("tx", Pins("DIO:0"), IOStandard("LVCMOS33")), # FTDI D1 - Subsignal("rx", Pins("INPUT:0"), IOStandard("LVCMOS33")) - ) # FTDI D0 -] - -leds = [ - ("user_led", 0, Pins("LED:0"), IOStandard("LVTTL")), - ("user_led", 1, Pins("LED:1"), IOStandard("LVTTL")), - ("user_led", 2, Pins("LED:2"), IOStandard("LVTTL")), - ("user_led", 3, Pins("LED:3"), IOStandard("LVTTL")) -] - -# See: http://www.micro-nova.com/mercury-baseboard/ -# Not implemented yet. -baseboard = [ -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk50" - default_clk_period = 20 - - def __init__(self, device="xc3s200a-4-vq100"): - XilinxPlatform.__init__(self, device, _io, _connectors) - # Small device- optimize for AREA instead of SPEED (LM32 runs at about - # 60-65MHz in AREA configuration). - self.toolchain.xst_opt = """-ifmt MIXED --use_new_parser yes --opt_mode AREA --register_balancing yes""" - - def create_programmer(self): - raise NotImplementedError diff --git a/mibuild/platforms/mimasv2.py b/mibuild/platforms/mimasv2.py deleted file mode 100644 index fd846569..00000000 --- a/mibuild/platforms/mimasv2.py +++ /dev/null @@ -1,124 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - - -_io = [ - ("clk100", 0, Pins("V10"), IOStandard("LVCMOS33")), - ("clk12", 0, Pins("D9"), IOStandard("LVCMOS33")), - - ("serial", 0, - Subsignal("tx", Pins("A8"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - Subsignal("rx", Pins("B8"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST"))), - - ("spiflash", 0, - Subsignal("cs_n", Pins("V3")), - Subsignal("clk", Pins("R15")), - Subsignal("mosi", Pins("T13")), - Subsignal("miso", Pins("R13"), Misc("PULLUP")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST")), - - ("ddram_clock", 0, - Subsignal("p", Pins("G3")), - Subsignal("n", Pins("G1")), - IOStandard("MOBILE_DDR")), - - ("ddram", 0, - Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")), - Subsignal("ba", Pins("F2 F1")), - Subsignal("cke", Pins("H7")), - Subsignal("ras_n", Pins("L5")), - Subsignal("cas_n", Pins("K5")), - Subsignal("we_n", Pins("E3")), - Subsignal( - "dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1") - ), - Subsignal("dqs", Pins("L4 P2")), - Subsignal("dm", Pins("K3 K4")), - IOStandard("MOBILE_DDR")), - - ("dipswitch", 0, Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("dipswitch", 1, Pins("C18"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("dipswitch", 2, Pins("D17"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("dipswitch", 3, Pins("D18"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("dipswitch", 4, Pins("E18"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("dipswitch", 5, Pins("E16"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("dipswitch", 6, Pins("F18"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("dipswitch", 7, Pins("F17"), IOStandard("LVCMOS33"), Misc("PULLUP")), - - ("buttonswitch", 0, Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("buttonswitch", 1, Pins("K17"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("buttonswitch", 2, Pins("L17"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("buttonswitch", 3, Pins("M16"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("buttonswitch", 4, Pins("L18"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("buttonswitch", 5, Pins("M18"), IOStandard("LVCMOS33"), Misc("PULLUP")), - - ("user_led", 0, Pins("T18"), IOStandard("LVCMOS33"), Drive(8)), - ("user_led", 1, Pins("T17"), IOStandard("LVCMOS33"), Drive(8)), - ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33"), Drive(8)), - ("user_led", 3, Pins("U17"), IOStandard("LVCMOS33"), Drive(8)), - ("user_led", 4, Pins("N16"), IOStandard("LVCMOS33"), Drive(8)), - ("user_led", 5, Pins("N15"), IOStandard("LVCMOS33"), Drive(8)), - ("user_led", 6, Pins("P16"), IOStandard("LVCMOS33"), Drive(8)), - ("user_led", 7, Pins("P15"), IOStandard("LVCMOS33"), Drive(8)), - - ("mmc", 0, - Subsignal("dat", Pins("K14 G18 J13 L13"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - - Subsignal("cmd", Pins("G16"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - - Subsignal("clk", Pins("L12"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST"))), - - ("sevenseg", 0, - Subsignal("segment7", Pins("A3"), IOStandard("LVCMOS33")), # A - Subsignal("segment6", Pins("B4"), IOStandard("LVCMOS33")), # B - Subsignal("segment5", Pins("A4"), IOStandard("LVCMOS33")), # C - Subsignal("segment4", Pins("C4"), IOStandard("LVCMOS33")), # D - Subsignal("segment3", Pins("C5"), IOStandard("LVCMOS33")), # E - Subsignal("segment2", Pins("D6"), IOStandard("LVCMOS33")), # F - Subsignal("segment1", Pins("C6"), IOStandard("LVCMOS33")), # G - Subsignal("segment0", Pins("A5"), IOStandard("LVCMOS33")), # Dot - Subsignal("enable0", Pins("B2"), IOStandard("LVCMOS33")), # EN0 - Subsignal("enable1", Pins("A2"), IOStandard("LVCMOS33")), # EN1 - Subsignal("enable2", Pins("B3"), IOStandard("LVCMOS33"))), # EN2 - - - ("audio", 0, - Subsignal("channel1", Pins("B16"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - Subsignal("channel2", Pins("A16"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST"))), - - ("vga_out", 0, - Subsignal("hsync_n", Pins("B12"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - Subsignal("vsync_n", Pins("A12"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - Subsignal("r", Pins("A9 B9 C9"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - Subsignal("g", Pins("C10 A10 C11"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST")), - Subsignal("b", Pins("B11 A11"), IOStandard("LVCMOS33"), - Misc("SLEW=FAST"))) -] - -_connectors = [ - ("P6", "T3 R3 V5 U5 V4 T4 V7 U7"), - ("P7", "V11 U11 V13 U13 T10 R10 T11 R11"), - ("P8", "L16 L15 K16 K15 J18 J16 H18 H17") -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk100" - default_clk_period = 10 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-csg324-2", _io, _connectors) - - def create_programmer(self): - raise NotImplementedError diff --git a/mibuild/platforms/minispartan6.py b/mibuild/platforms/minispartan6.py deleted file mode 100644 index 843fa3d5..00000000 --- a/mibuild/platforms/minispartan6.py +++ /dev/null @@ -1,125 +0,0 @@ -# This file is Copyright (c) 2015 Matt O'Gorman -# License: BSD - -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform -from mibuild.xilinx.programmer import XC3SProg, FpgaProg - -_io = [ - ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("N9"), IOStandard("LVCMOS33")), - ("user_led", 2, Pins("M9"), IOStandard("LVCMOS33")), - ("user_led", 3, Pins("P9"), IOStandard("LVCMOS33")), - ("user_led", 4, Pins("T8"), IOStandard("LVCMOS33")), - ("user_led", 5, Pins("N8"), IOStandard("LVCMOS33")), - ("user_led", 6, Pins("P8"), IOStandard("LVCMOS33")), - ("user_led", 7, Pins("P7"), IOStandard("LVCMOS33")), - - ("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")), - - ("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")), - ("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")), - - ("spiflash", 0, - Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")), - Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")), - Subsignal("mosi", Pins("T10"), IOStandard("LVCMOS33")), - Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33")) - ), - - ("adc", 0, - Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")), - Subsignal("clk", Pins("G6"), IOStandard("LVCMOS33")), - Subsignal("mosi", Pins("H4"), IOStandard("LVCMOS33")), - Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33")) - ), - - ("serial", 0, - Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1 - Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0 - ), - - ("audio", 0, - Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")), - Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33")) - ), - - ("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), - ("sdram", 0, - Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")), - Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")), - Subsignal("we_n", Pins("R5")), - Subsignal("ras_n", Pins("R2")), - Subsignal("cas_n", Pins("T4")), - Subsignal("cs_n", Pins("R1")), - Subsignal("cke", Pins("H16")), - Subsignal("ba", Pins("R14 T14")), - Subsignal("dm", Pins("T5 F15")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") - ), - - ("usb_fifo", 0, - Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")), - Subsignal("rxf_n", Pins("N3")), - Subsignal("txe_n", Pins("N1")), - Subsignal("rd_n", Pins("M1")), - Subsignal("wr_n", Pins("M2")), - Subsignal("siwua", Pins("M3")), - IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST") - ), - - ("sd", 0, - Subsignal("sck", Pins("L12")), - Subsignal("d3", Pins("K12")), - Subsignal("d", Pins("M10")), - Subsignal("d1", Pins("L10")), - Subsignal("d2", Pins("J11")), - Subsignal("cmd", Pins("K11")), - IOStandard("LVCMOS33") - ), - - ("dvi_in", 0, - Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")), - Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")), - Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33")) - ), - - ("dvi_out", 0, - Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")), - Subsignal("data_p", Pins("C13 B12 C11"), IOStandard("TMDS_33")), - Subsignal("data_n", Pins("A13 A12 A11"), IOStandard("TMDS_33")), - ) -] - -_connectors = [ - ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"), - ("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"), - ("C", "J13 J12 K14 L14 L13 M14 M13 N14 M12 N12 P12 M11"), - ("D", "D6 C6 E6 C5"), - ("E", "D5 A4 G5 A3 B3 A2 B2 C3 C2 D3 D1 E3"), - ("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1") -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk32" - default_clk_period = 31.25 - - def __init__(self, device="xc6slx9", programmer="xc3sprog"): - self.programmer = programmer - XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) - - def create_programmer(self): - if self.programmer == "xc3sprog": - return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit") - elif self.programmer == "fpgaprog": - return FpgaProg() - else: - raise ValueError("{} programmer is not supported".format(programmer)) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py deleted file mode 100644 index 69096e54..00000000 --- a/mibuild/platforms/mixxeo.py +++ /dev/null @@ -1,187 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform -from mibuild.xilinx.programmer import UrJTAG - -_io = [ - ("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), - - ("clk50", 0, Pins("AB13"), IOStandard("LVCMOS33")), - - # When executing softcore code in-place from the flash, we want - # the flash reset to be released before the system reset. - ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), - ("norflash", 0, - Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22", - "F21 K17 J17 E22 E20 H18 H19 F20", - "G19 C22 C20 D22 D21 F19 F18 D20 D19")), - Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7", - "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")), - Subsignal("oe_n", Pins("M22")), - Subsignal("we_n", Pins("N20")), - Subsignal("ce_n", Pins("M21")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8) - ), - - ("serial", 0, - Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), - Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")) - ), - - ("ddram_clock", 0, - Subsignal("p", Pins("M3")), - Subsignal("n", Pins("L4")), - IOStandard("SSTL2_I") - ), - ("ddram", 0, - Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")), - Subsignal("ba", Pins("A2 E6")), - Subsignal("cs_n", Pins("F7")), - Subsignal("cke", Pins("G7")), - Subsignal("ras_n", Pins("E5")), - Subsignal("cas_n", Pins("C4")), - Subsignal("we_n", Pins("D3")), - Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3", - "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4", - "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")), - Subsignal("dm", Pins("E1 E3 F3 G4")), - Subsignal("dqs", Pins("F1 F2 H5 H6")), - IOStandard("SSTL2_I") - ), - - ("eth_clocks", 0, - Subsignal("phy", Pins("M20")), - Subsignal("rx", Pins("H22")), - Subsignal("tx", Pins("H21")), - IOStandard("LVCMOS33") - ), - ("eth", 0, - Subsignal("rst_n", Pins("R22")), - Subsignal("dv", Pins("V21")), - Subsignal("rx_er", Pins("V22")), - Subsignal("rx_data", Pins("U22 U20 T22 T21")), - Subsignal("tx_en", Pins("N19")), - Subsignal("tx_er", Pins("M19")), - Subsignal("tx_data", Pins("M16 L15 P19 P20")), - Subsignal("col", Pins("W20")), - Subsignal("crs", Pins("W22")), - IOStandard("LVCMOS33") - ), - - ("vga_out", 0, - Subsignal("clk", Pins("A10")), - Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), - Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), - Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")), - Subsignal("hsync_n", Pins("A14")), - Subsignal("vsync_n", Pins("C15")), - Subsignal("psave_n", Pins("B14")), - IOStandard("LVCMOS33") - ), - ("dvi_out", 0, - Subsignal("clk_p", Pins("W12"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("Y12"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("Y16"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("W15"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("AA16"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("AB16"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("Y15"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("AB15"), IOStandard("TMDS_33")), - ), - - ("mmc", 0, - Subsignal("clk", Pins("J3")), - Subsignal("cmd", Pins("K1")), - Subsignal("dat", Pins("J6 K6 N1 K5")), - IOStandard("LVCMOS33") - ), - - ("dvi_in", 0, - Subsignal("clk_p", Pins("K20"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("K19"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("B21"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("B22"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("A20"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("A21"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("K16"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("J16"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("G20"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("H16"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33")) - ), - ("dvi_in", 1, - Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("A11"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("B18"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("A18"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("C17"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("A17"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("F17"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("F16"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33")) - ), - ("dvi_in", 2, - Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("AB11"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("V11"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("W11"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("AA10"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("AB10"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("R11"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("T11"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("C16"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("B16"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("D6"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("A4"), IOStandard("LVCMOS33")) - ), - ("dvi_in", 3, - Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("J22"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("P18"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("R19"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("P17"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("N16"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("M17"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("M18"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("P21"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("N22"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("H17"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("C19"), IOStandard("LVCMOS33")) - ), -] - - -class Platform(XilinxPlatform): - identifier = 0x4D58 - default_clk_name = "clk50" - default_clk_period = 20 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io) - self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") - - def create_programmer(self): - return UrJTAG("fjmem-mixxeo.bit") - - def do_finalize(self, fragment): - XilinxPlatform.do_finalize(self, fragment) - - try: - eth_clocks = self.lookup_request("eth_clocks") - self.add_period_constraint(eth_clocks.rx, 40) - self.add_period_constraint(eth_clocks.tx, 40) - self.add_platform_command(""" -TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; -TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; -""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) - except ConstraintError: - pass - - for i in range(4): - try: - self.add_period_constraint(self.lookup_request("dvi_in", i).clk_p, 12) - except ConstraintError: - pass diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py deleted file mode 100644 index 26ac49fc..00000000 --- a/mibuild/platforms/ml605.py +++ /dev/null @@ -1,59 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_io = [ - # System clock (Differential 200MHz) - ("clk200", 0, - Subsignal("p", Pins("J9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), - Subsignal("n", Pins("H9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")) - ), - - # User clock (66MHz) - ("clk66", 0, Pins("U23"), IOStandard("LVCMOS25")), - - # CPU reset switch - ("cpu_reset", 0, Pins("H10"), IOStandard("SSTL15")), - - # LEDs - ("user_led", 0, Pins("AC22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - ("user_led", 1, Pins("AC24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - ("user_led", 2, Pins("AE22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - ("user_led", 3, Pins("AE23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - ("user_led", 4, Pins("AB23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - ("user_led", 5, Pins("AG23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - ("user_led", 6, Pins("AE24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - ("user_led", 7, Pins("AD24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), - - # USB-to-UART - ("serial", 0, - Subsignal("tx", Pins("J25"), IOStandard("LVCMOS25")), - Subsignal("rx", Pins("J24"), IOStandard("LVCMOS25")) - ), - - # 10/100/1000 Tri-Speed Ethernet PHY - ("eth_clocks", 0, - Subsignal("rx", Pins("AP11")), - Subsignal("tx", Pins("AD12")), - IOStandard("LVCMOS25") - ), - ("eth", 0, - Subsignal("rst_n", Pins("AH13")), - Subsignal("dv", Pins("AM13")), - Subsignal("rx_er", Pins("AG12")), - Subsignal("rx_data", Pins("AN13 AF14 AE14 AN12 AM12 AD11 AC12 AC13")), - Subsignal("tx_en", Pins("AJ10")), - Subsignal("tx_er", Pins("AH10")), - Subsignal("tx_data", Pins("AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11")), - Subsignal("col", Pins("AK13")), - Subsignal("crs", Pins("AL13")), - IOStandard("LVCMOS25") - ) -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk200" - default_clk_period = 5 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io) diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py deleted file mode 100644 index 5d35c7a3..00000000 --- a/mibuild/platforms/papilio_pro.py +++ /dev/null @@ -1,61 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform -from mibuild.xilinx.programmer import XC3SProg - -_io = [ - ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), - - ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")), - - ("serial", 0, - Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), - Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP")) - ), - - ("spiflash", 0, - Subsignal("cs_n", Pins("P38")), - Subsignal("clk", Pins("P70")), - Subsignal("mosi", Pins("P64")), - Subsignal("miso", Pins("P65"), Misc("PULLUP")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") - ), - ("spiflash2x", 0, - Subsignal("cs_n", Pins("P38")), - Subsignal("clk", Pins("P70")), - Subsignal("dq", Pins("P64", "P65")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") - ), - - ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), - ("sdram", 0, - Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44", - "P43 P41 P40 P141 P35 P34")), - Subsignal("ba", Pins("P143 P142")), - Subsignal("cs_n", Pins("P1")), - Subsignal("cke", Pins("P33")), - Subsignal("ras_n", Pins("P2")), - Subsignal("cas_n", Pins("P5")), - Subsignal("we_n", Pins("P6")), - Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")), - Subsignal("dm", Pins("P7 P17")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") - ) -] - -_connectors = [ - ("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"), - ("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"), - ("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134") -] - - -class Platform(XilinxPlatform): - identifier = 0x5050 - default_clk_name = "clk32" - default_clk_period = 31.25 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors) - - def create_programmer(self): - return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit") diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py deleted file mode 100644 index 072bcf20..00000000 --- a/mibuild/platforms/pipistrello.py +++ /dev/null @@ -1,137 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform -from mibuild.xilinx.programmer import XC3SProg - -_io = [ - ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi - ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi - ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd - ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd - ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb - - ("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")), - - ("clk50", 0, Pins("H17"), IOStandard("LVTTL")), - - ("serial", 0, - Subsignal("tx", Pins("A10")), - Subsignal("rx", Pins("A11"), Misc("PULLUP")), - Subsignal("cts", Pins("C10"), Misc("PULLUP")), - Subsignal("rts", Pins("A9"), Misc("PULLUP")), - IOStandard("LVTTL"), - ), - - ("usb_fifo", 0, - Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")), - Subsignal("rxf_n", Pins("C7")), - Subsignal("txe_n", Pins("A6")), - Subsignal("rd_n", Pins("B6")), - Subsignal("wr_n", Pins("A5")), - Subsignal("siwua", Pins("C5")), - IOStandard("LVTTL"), - ), - - ("hdmi", 0, - Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("T6"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("V6"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("U7"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("V7"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("U8"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("V8"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("V9"), IOStandard("I2C")), - Subsignal("sda", Pins("T9"), IOStandard("I2C")), - Subsignal("hpd_notif", Pins("R8"), IOStandard("LVTTL")), - ), - - ("spiflash", 0, - Subsignal("cs_n", Pins("V3")), - Subsignal("clk", Pins("R15")), - Subsignal("mosi", Pins("T13")), - Subsignal("miso", Pins("R13"), Misc("PULLUP")), - Subsignal("wp", Pins("T14")), - Subsignal("hold", Pins("V14")), - IOStandard("LVTTL"), Misc("SLEW=FAST") - ), - - ("spiflash2x", 0, - Subsignal("cs_n", Pins("V3")), - Subsignal("clk", Pins("R15")), - Subsignal("dq", Pins("T13 R13"), Misc("PULLUP")), - Subsignal("wp", Pins("T14")), - Subsignal("hold", Pins("V14")), - IOStandard("LVTTL"), Misc("SLEW=FAST") - ), - - ("spiflash4x", 0, - Subsignal("cs_n", Pins("V3")), - Subsignal("clk", Pins("R15")), - Subsignal("dq", Pins("T13 R13 T14 V14"), Misc("PULLUP")), - IOStandard("LVTTL"), Misc("SLEW=FAST") - ), - - ("mmc", 0, - Subsignal("clk", Pins("A3")), - Subsignal("cmd", Pins("B3"), Misc("PULLUP")), - Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")), - IOStandard("SDIO") - ), - - ("mmc_spi", 0, - Subsignal("cs_n", Pins("A2"), Misc("PULLUP")), - Subsignal("clk", Pins("A3")), - Subsignal("mosi", Pins("B3")), - Subsignal("miso", Pins("B4"), Misc("PULLUP")), - IOStandard("SDIO") - ), - - ("audio", 0, - Subsignal("l", Pins("R7"), Misc("SLEW=SLOW")), - Subsignal("r", Pins("T7"), Misc("SLEW=SLOW")), - IOStandard("LVTTL"), - ), - - ("pmod", 0, - Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")), - IOStandard("LVTTL") - ), - - ("ddram_clock", 0, - Subsignal("p", Pins("G3")), - Subsignal("n", Pins("G1")), - IOStandard("MOBILE_DDR") - ), - - ("ddram", 0, - Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")), - Subsignal("ba", Pins("F2 F1")), - Subsignal("cke", Pins("H7")), - Subsignal("ras_n", Pins("L5")), - Subsignal("cas_n", Pins("K5")), - Subsignal("we_n", Pins("E3")), - Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")), - Subsignal("dqs", Pins("L4 P2")), - Subsignal("dm", Pins("K3 K4")), - IOStandard("MOBILE_DDR") - ) -] - -_connectors = [ - ("A", "U18 T17 P17 P16 N16 N17 M16 L15 L17 K15 K17 J16 H15 H18 F18 D18"), - ("B", "C18 E18 G18 H16 J18 K18 K16 L18 L16 M18 N18 N15 P15 P18 T18 U17"), - ("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"), -] - - -class Platform(XilinxPlatform): - identifier = 0x5049 - default_clk_name = "clk50" - default_clk_period = 20 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors) - self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6" - - def create_programmer(self): - return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit") diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py deleted file mode 100644 index 5f766ff9..00000000 --- a/mibuild/platforms/rhino.py +++ /dev/null @@ -1,141 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_io = [ - ("user_led", 0, Pins("Y3")), - ("user_led", 1, Pins("Y1")), - ("user_led", 2, Pins("W2")), - ("user_led", 3, Pins("W1")), - ("user_led", 4, Pins("V3")), - ("user_led", 5, Pins("V1")), - ("user_led", 6, Pins("U2")), - ("user_led", 7, Pins("U1")), - - ("clk100", 0, - Subsignal("p", Pins("B14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), - Subsignal("n", Pins("A14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")) - ), - - ("gpio", 0, Pins("R8")), - - ("gpmc", 0, - Subsignal("clk", Pins("R26")), - Subsignal("a", Pins("N17 N18 L23 L24 N19 N20 N21 N22 P17 P19")), - Subsignal("d", Pins("N23 N24 R18 R19 P21 P22 R20 R21 P24 P26 R23 R24 T22 T23 U23 R25")), - Subsignal("we_n", Pins("W26")), - Subsignal("oe_n", Pins("AA25")), - Subsignal("ale_n", Pins("AA26")), - Subsignal("wait", Pins("AD26")), # WAIT1/BUSY0 - IOStandard("LVCMOS33")), - # Warning: CS are numbered 1-7 on ARM side and 0-6 on FPGA side. - # Numbers here are given on the FPGA side. - ("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")), # nCS0 - ("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")), # nCS1 - ("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")), # nCS6 - ("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")), # nCS2 - ("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")), # nCS3 - ("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")), # nCS4 - ("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")), # nCS5 - - # FMC150 - ("fmc150_ctrl", 0, - Subsignal("spi_sclk", Pins("AE5")), - Subsignal("spi_data", Pins("AF5")), - - Subsignal("adc_sdo", Pins("U13")), - Subsignal("adc_en_n", Pins("AA15")), - Subsignal("adc_reset", Pins("V13")), - - Subsignal("cdce_sdo", Pins("AA8")), - Subsignal("cdce_en_n", Pins("Y9")), - Subsignal("cdce_reset_n", Pins("AB7")), - Subsignal("cdce_pd_n", Pins("AC6")), - Subsignal("cdce_pll_status", Pins("W7")), - Subsignal("cdce_ref_en", Pins("W8")), - - Subsignal("dac_sdo", Pins("W9")), - Subsignal("dac_en_n", Pins("W10")), - - Subsignal("mon_sdo", Pins("AC5")), - Subsignal("mon_en_n", Pins("AD6")), - Subsignal("mon_reset_n", Pins("AF6")), - Subsignal("mon_int_n", Pins("AD5")), - - Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33")) - ), - ("ti_dac", 0, # DAC3283 - Subsignal("dat_p", Pins("AA10 AA9 V11 Y11 W14 Y12 AD14 AE13"), IOStandard("LVDS_25")), - Subsignal("dat_n", Pins("AB11 AB9 V10 AA11 Y13 AA12 AF14 AF13"), IOStandard("LVDS_25")), - Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")), - Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")), - Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25")) - ), - ("ti_adc", 0, # ADS62P49 - Subsignal("dat_a_p", Pins("AB14 Y21 W20 AB22 V18 W17 AA21")), - Subsignal("dat_a_n", Pins("AC14 AA22 Y20 AC22 W19 W18 AB21")), - Subsignal("dat_b_p", Pins("Y17 U15 AA19 W16 AA18 Y15 V14")), - Subsignal("dat_b_n", Pins("AA17 V16 AB19 Y16 AB17 AA16 V15")), - IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE") - ), - ("fmc150_clocks", 0, - Subsignal("dac_clk_p", Pins("V12"), IOStandard("LVDS_25")), - Subsignal("dac_clk_n", Pins("W12"), IOStandard("LVDS_25")), - Subsignal("adc_clk_p", Pins("AE15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), - Subsignal("adc_clk_n", Pins("AF15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), - Subsignal("clk_to_fpga", Pins("W24"), IOStandard("LVCMOS25")) - ), - - ("fmc150_ext_trigger", 0, Pins("U26")), - - # Vermeer radar testbed - # Switch controller - ("pca9555", 0, - Subsignal("sda", Pins("C13")), - Subsignal("scl", Pins("G8")), - IOStandard("LVCMOS33") - ), - # TX path - ("pe43602", 0, - Subsignal("d", Pins("H8")), - Subsignal("clk", Pins("B3")), - Subsignal("le", Pins("F7")), - IOStandard("LVCMOS33") - ), - ("rfmd2081", 0, - Subsignal("enx", Pins("E5")), - Subsignal("sclk", Pins("G6")), - Subsignal("sdata", Pins("F5")), - Subsignal("locked", Pins("E6")), - IOStandard("LVCMOS33") - ), - # RX path - ("lmh6521", 0, - Subsignal("scsb", Pins("C5")), - Subsignal("sclk", Pins("G10")), - Subsignal("sdi", Pins("D5")), - Subsignal("sdo", Pins("F9")), - IOStandard("LVCMOS33") - ), - ("lmh6521", 1, - Subsignal("scsb", Pins("E10")), - Subsignal("sclk", Pins("A4")), - Subsignal("sdi", Pins("B4")), - Subsignal("sdo", Pins("H10")), - IOStandard("LVCMOS33") - ), - ("rffc5071", 0, - Subsignal("enx", Pins("A2")), - Subsignal("sclk", Pins("G9")), - Subsignal("sdata", Pins("H9")), - Subsignal("locked", Pins("A3")), - IOStandard("LVCMOS33") - ) -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk100" - default_clk_period = 10 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io) diff --git a/mibuild/platforms/roach.py b/mibuild/platforms/roach.py deleted file mode 100644 index 66f81337..00000000 --- a/mibuild/platforms/roach.py +++ /dev/null @@ -1,34 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_io = [ - ("epb", 0, - Subsignal("cs_n", Pins("K13")), - Subsignal("r_w_n", Pins("AF20")), - Subsignal("be_n", Pins("AF14 AF18")), - Subsignal("oe_n", Pins("AF21")), - Subsignal("addr", Pins("AE23 AE22 AG18 AG12 AG15 AG23 AF19 AE12 AG16 AF13 AG20 AF23", - "AH17 AH15 L20 J22 H22 L15 L16 K22 K21 K16 J15")), - Subsignal("addr_gp", Pins("L21 G22 K23 K14 L14 J12")), - Subsignal("data", Pins("AF15 AE16 AE21 AD20 AF16 AE17 AE19 AD19 AG22 AH22 AH12 AG13", - "AH20 AH19 AH14 AH13")), - Subsignal("rdy", Pins("K12")), - IOStandard("LVCMOS33") - ), - ("roach_clocks", 0, - Subsignal("epb_clk", Pins("AH18"), IOStandard("LVCMOS33")), - Subsignal("sys_clk_n", Pins("H13")), - Subsignal("sys_clk_p", Pins("J14")), - Subsignal("aux0_clk_p", Pins("G15")), - Subsignal("aux0_clk_n", Pins("G16")), - Subsignal("aux1_clk_p", Pins("H14")), - Subsignal("aux1_clk_n", Pins("H15")), - Subsignal("dly_clk_n", Pins("J17")), - Subsignal("dly_clk_p", Pins("J16")), - ), -] - - -class Platform(XilinxPlatform): - def __init__(self): - XilinxPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io) diff --git a/mibuild/platforms/sim.py b/mibuild/platforms/sim.py deleted file mode 100644 index 55dec467..00000000 --- a/mibuild/platforms/sim.py +++ /dev/null @@ -1,45 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.sim import SimPlatform - - -class SimPins(Pins): - def __init__(self, n): - Pins.__init__(self, "s "*n) - -_io = [ - ("sys_clk", 0, SimPins(1)), - ("sys_rst", 0, SimPins(1)), - ("serial", 0, - Subsignal("source_stb", SimPins(1)), - Subsignal("source_ack", SimPins(1)), - Subsignal("source_data", SimPins(8)), - - Subsignal("sink_stb", SimPins(1)), - Subsignal("sink_ack", SimPins(1)), - Subsignal("sink_data", SimPins(8)), - ), - ("eth_clocks", 0, - Subsignal("none", SimPins(1)), - ), - ("eth", 0, - Subsignal("source_stb", SimPins(1)), - Subsignal("source_ack", SimPins(1)), - Subsignal("source_data", SimPins(8)), - - Subsignal("sink_stb", SimPins(1)), - Subsignal("sink_ack", SimPins(1)), - Subsignal("sink_data", SimPins(8)), - ), -] - - -class Platform(SimPlatform): - is_sim = True - default_clk_name = "sys_clk" - default_clk_period = 1000 # on modern computers simulate at ~ 1MHz - - def __init__(self): - SimPlatform.__init__(self, "SIM", _io) - - def do_finalize(self, fragment): - pass diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py deleted file mode 100644 index 6448a6cc..00000000 --- a/mibuild/platforms/usrp_b100.py +++ /dev/null @@ -1,151 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_io = [ - ("clk64", 0, - Subsignal("p", Pins("R7")), - Subsignal("n", Pins("T7")), - IOStandard("LVDS_33"), - Misc("DIFF_TERM=TRUE"), - ), - - ("pps", 0, Pins("M14"), Misc("TIG")), - ("reset_n", 0, Pins("D5"), Misc("TIG")), - ("codec_reset", 0, Pins("B14")), - # recycles fpga_cfg_cclk for reset from fw - ("ext_reset", 0, Pins("R14")), - - ("i2c", 0, - Subsignal("sda", Pins("T13")), - Subsignal("scl", Pins("R13")), - ), - - ("cgen", 0, - Subsignal("st_ld", Pins("M13")), - Subsignal("st_refmon", Pins("J14")), - Subsignal("st_status", Pins("P6")), - Subsignal("ref_sel", Pins("T2")), - Subsignal("sync_b", Pins("H15")), - ), - - ("fx2_ifclk", 0, Pins("T8")), - ("fx2_gpif", 0, - Subsignal("d", Pins("P8 P9 N9 T9 R9 P11 P13 N12 " - "T3 R3 P5 N6 T6 T5 N8 P7")), - Subsignal("ctl", Pins("M7 M9 M11 P12")), - Subsignal("slwr", Pins("T4")), # rdy0 - Subsignal("slrd", Pins("R5")), # rdy1 - # Subsignal("rdy2", Pins("T10")), - # Subsignal("rdy3", Pins("N11")), - # Subsignal("cs", Pins("P12")), - Subsignal("sloe", Pins("R11")), - Subsignal("pktend", Pins("P10")), - Subsignal("adr", Pins("T11 H16")), - ), - - ("user_led", 0, Pins("P4"), Misc("TIG")), - ("user_led", 1, Pins("N4"), Misc("TIG")), - ("user_led", 2, Pins("R2"), Misc("TIG")), - - ("debug_clk", 0, Pins("K15 K14")), - ("debug", 0, Pins( - "K16 J16 C16 C15 E13 D14 D16 D15 " - "E14 F13 G13 F14 E16 F15 H13 G14 " - "G16 F16 J12 J13 L14 L16 M15 M16 " - "L13 K13 P16 N16 R15 P15 N13 N14")), - - ("adc", 0, - Subsignal("sync", Pins("D10")), - Subsignal("d", Pins("A4 B3 A3 D9 C10 A9 C9 D8 " - "C8 B8 A8 B15")), - ), - ("dac", 0, - Subsignal("blank", Pins("K1")), - Subsignal("sync", Pins("J2")), - Subsignal("d", Pins("J1 H3 J3 G2 H1 N3 M4 R1 " - "P2 P1 M1 N1 M3 L4")), - ), - ("codec_spi", 0, - Subsignal("sclk", Pins("K3")), - Subsignal("sen", Pins("D13")), - Subsignal("mosi", Pins("C13")), - Subsignal("miso", Pins("G4")), - ), - - ("aux_spi", 0, - Subsignal("sen", Pins("C12")), - Subsignal("sclk", Pins("D12")), - Subsignal("miso", Pins("J5")), - ), - ("rx_io", 0, Pins("D7 C6 A6 B6 E9 A7 C7 B10 " - "A10 C11 A11 D11 B12 A12 A14 A13")), - ("tx_io", 0, Pins("K4 L3 L2 F1 F3 G3 E3 E2 " - "E4 F4 D1 E1 D4 D3 C2 C1")), - ("rx_spi", 0, - Subsignal("miso", Pins("E6")), - Subsignal("sen", Pins("B4")), - Subsignal("mosi", Pins("A5")), - Subsignal("sclk", Pins("C5")), - ), - ("tx_spi", 0, - Subsignal("miso", Pins("J4")), - Subsignal("sen", Pins("N2")), - Subsignal("mosi", Pins("L1")), - Subsignal("sclk", Pins("G1")), - ), - - # these are just for information. do not request. - ("mystery_bus", 0, Pins("C4 E7")), - ("fpga_cfg", - Subsignal("din", Pins("T14")), - Subsignal("cclk", Pins("R14")), - Subsignal("init_b", Pins("T12")), - Subsignal("prog_b", Pins("A2")), - Subsignal("done", Pins("T15")), - ), - ("jtag", - Subsignal("tms", Pins("B2")), - Subsignal("tdo", Pins("B16")), - Subsignal("tdi", Pins("B1")), - Subsignal("tck", Pins("A15")), - ), -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk64" - default_clk_period = 15.625 - - def __init__(self): - XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io) - self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp" - - def do_finalize(self, fragment): - XilinxPlatform.do_finalize(self, fragment) - - self.add_platform_command(""" -TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; -""") - - try: - ifclk = self.lookup_request("fx2_ifclk") - gpif = self.lookup_request("fx2_gpif") - for i, d in [(gpif.d, "in"), (gpif.d, "out"), - (gpif.ctl, "in"), (gpif.adr, "out"), - (gpif.slwr, "out"), (gpif.sloe, "out"), - (gpif.slrd, "out"), (gpif.pktend, "out")]: - if flen(i) > 1: - q = "(*)" - else: - q = "" - self.add_platform_command(""" -INST "{i}%s" TNM = gpif_net_%s; -""" % (q, d), i=i) - self.add_platform_command(""" -NET "{ifclk}" TNM_NET = "GRPifclk"; -TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%; -TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING; -TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING; -""", ifclk=ifclk) - except ConstraintError: - pass diff --git a/mibuild/platforms/versa.py b/mibuild/platforms/versa.py deleted file mode 100644 index e164bdec..00000000 --- a/mibuild/platforms/versa.py +++ /dev/null @@ -1,95 +0,0 @@ -# This file is Copyright (c) 2013 Florent Kermarrec -# License: BSD - -from mibuild.generic_platform import * -from mibuild.lattice import LatticePlatform -from mibuild.lattice.programmer import LatticeProgrammer - -_io = [ - ("clk100", 0, Pins("L5"), IOStandard("LVDS25")), - ("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")), - - ("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")), - ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")), - ("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")), - ("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")), - ("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")), - ("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")), - ("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")), - - ("user_dip_btn", 0, Pins("J7"), IOStandard("LVCMOS15")), - ("user_dip_btn", 1, Pins("J6"), IOStandard("LVCMOS15")), - ("user_dip_btn", 2, Pins("H2"), IOStandard("LVCMOS15")), - ("user_dip_btn", 3, Pins("H3"), IOStandard("LVCMOS15")), - ("user_dip_btn", 4, Pins("J3"), IOStandard("LVCMOS15")), - ("user_dip_btn", 5, Pins("K3"), IOStandard("LVCMOS15")), - ("user_dip_btn", 6, Pins("J2"), IOStandard("LVCMOS15")), - ("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")), - - ("serial", 0, - Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")), # X4 IO0 - Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")), # X4 IO1 - ), - - ("eth_clocks", 0, - Subsignal("tx", Pins("C12")), - Subsignal("gtx", Pins("M2")), - Subsignal("rx", Pins("L4")), - IOStandard("LVCMOS33") - ), - ("eth", 0, - Subsignal("rst_n", Pins("L3")), - Subsignal("mdio", Pins("L2")), - Subsignal("mdc", Pins("V4")), - Subsignal("dv", Pins("M1")), - Subsignal("rx_er", Pins("M4")), - Subsignal("rx_data", Pins("M5 N1 N6 P6 T2 R2 P5 P3")), - Subsignal("tx_en", Pins("V3")), - Subsignal("tx_data", Pins("V1 U1 R3 P1 N5 N3 N4 N2")), - Subsignal("col", Pins("R1")), - Subsignal("crs", Pins("P4")), - IOStandard("LVCMOS33") - ), - - ("eth_clocks", 1, - Subsignal("tx", Pins("M21")), - Subsignal("gtx", Pins("M19")), - Subsignal("rx", Pins("N19")), - IOStandard("LVCMOS33") - ), - ("eth", 1, - Subsignal("rst_n", Pins("R21")), - Subsignal("mdio", Pins("U16")), - Subsignal("mdc", Pins("Y18")), - Subsignal("dv", Pins("U15")), - Subsignal("rx_er", Pins("V20")), - Subsignal("rx_data", Pins("AB17 AA17 R19 V21 T17 R18 W21 Y21")), - Subsignal("tx_en", Pins("V22")), - Subsignal("tx_data", Pins("W22 R16 P17 Y22 T21 U22 P20 U20")), - Subsignal("col", Pins("N18")), - Subsignal("crs", Pins("P19")), - IOStandard("LVCMOS33") - ), -] - - -class Platform(LatticePlatform): - default_clk_name = "clk100" - default_clk_period = 10 - - def __init__(self): - LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io) - - def do_finalize(self, fragment): - LatticePlatform.do_finalize(self, fragment) - try: - self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0) - except ConstraintError: - pass - def create_programmer(self): - return LatticeProgrammer() diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py deleted file mode 100644 index 72a799aa..00000000 --- a/mibuild/platforms/zedboard.py +++ /dev/null @@ -1,144 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -# Bank 34 and 35 voltage depend on J18 jumper setting -_io = [ - ("clk100", 0, Pins("Y9"), IOStandard("LVCMOS33")), - - ("user_btn", 0, Pins("P16"), IOStandard("LVCMOS18")), # center - ("user_btn", 1, Pins("R16"), IOStandard("LVCMOS18")), # down - ("user_btn", 2, Pins("N15"), IOStandard("LVCMOS18")), # left - ("user_btn", 3, Pins("R18"), IOStandard("LVCMOS18")), # right - ("user_btn", 4, Pins("T18"), IOStandard("LVCMOS18")), # up - - ("user_sw", 0, Pins("F22"), IOStandard("LVCMOS18")), - ("user_sw", 1, Pins("G22"), IOStandard("LVCMOS18")), - ("user_sw", 2, Pins("H22"), IOStandard("LVCMOS18")), - ("user_sw", 3, Pins("F21"), IOStandard("LVCMOS18")), - ("user_sw", 4, Pins("H19"), IOStandard("LVCMOS18")), - ("user_sw", 5, Pins("H18"), IOStandard("LVCMOS18")), - ("user_sw", 6, Pins("H17"), IOStandard("LVCMOS18")), - ("user_sw", 7, Pins("M15"), IOStandard("LVCMOS18")), - - ("user_led", 0, Pins("T22"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("T21"), IOStandard("LVCMOS33")), - ("user_led", 2, Pins("U22"), IOStandard("LVCMOS33")), - ("user_led", 3, Pins("U21"), IOStandard("LVCMOS33")), - ("user_led", 4, Pins("V22"), IOStandard("LVCMOS33")), - ("user_led", 5, Pins("W22"), IOStandard("LVCMOS33")), - ("user_led", 6, Pins("U19"), IOStandard("LVCMOS33")), - ("user_led", 7, Pins("U14"), IOStandard("LVCMOS33")), - - # A - ("pmod", 0, Pins("Y11 AA11 Y10 AA9 AB11 AB10 AB9 AA8"), - IOStandard("LVCMOS33")), - # B - ("pmod", 1, Pins("W12 W11 V10 W8 V12 W10 V9 V8"), - IOStandard("LVCMOS33")), - # C - ("pmod", 2, - Subsignal("n", Pins("AB6 AA4 T6 U4")), - Subsignal("p", Pins("AB7 Y4 R6 T4")), - IOStandard("LVCMOS33")), - # D - ("pmod", 3, - Subsignal("n", Pins("W7 V4 W5 U5")), - Subsignal("p", Pins("V7 V5 W6 U6")), - IOStandard("LVCMOS33")), - - ("audio", 0, - Subsignal("adr", Pins("AB1 Y5")), - Subsignal("gpio", Pins("Y8 AA7 AA6 Y6")), - Subsignal("mclk", Pins("AB2")), - Subsignal("sck", Pins("AB4")), - Subsignal("sda", Pins("AB5")), - IOStandard("LVCMOS33")), - - ("oled", 0, - Subsignal("dc", Pins("U10")), - Subsignal("res", Pins("U9")), - Subsignal("sclk", Pins("AB12")), - Subsignal("sdin", Pins("AA12")), - Subsignal("vbat", Pins("U11")), - Subsignal("vdd", Pins("U12")), - IOStandard("LVCMOS33")), - - ("hdmi", 0, - Subsignal("clk", Pins("W18")), - Subsignal("d", Pins( - "Y13 AA13 AA14 Y14 AB15 AB16 AA16 AB17 " - "AA17 Y15 W13 W15 V15 U17 V14 V13")), - Subsignal("de", Pins("U16")), - Subsignal("hsync", Pins("V17")), - Subsignal("vsync", Pins("W17")), - Subsignal("int", Pins("W16")), - Subsignal("scl", Pins("AA18")), - Subsignal("sda", Pins("Y16")), - Subsignal("spdif", Pins("U15")), - Subsignal("spdifo", Pins("Y18")), - IOStandard("LVCMOS33")), - - ("netic16", 0, - Subsignal("w20", Pins("W20")), - Subsignal("w21", Pins("W21")), - IOStandard("LVCMOS33")), - - ("vga", 0, - Subsignal("r", Pins("V20 U20 V19 V18")), - Subsignal("g", Pins("AB22 AA22 AB21 AA21")), - Subsignal("b", Pins("Y21 Y20 AB20 AB19")), - Subsignal("hsync_n", Pins("AA19")), - Subsignal("vsync_n", Pins("Y19")), - IOStandard("LVCMOS33")), - - ("usb_otg", 0, - Subsignal("vbusoc", Pins("L16")), - Subsignal("reset_n", Pins("G17")), - IOStandard("LVCMOS18")), - - ("pudc_b", 0, Pins("K16"), IOStandard("LVCMOS18")), - - ("xadc", 0, - Subsignal("gio", Pins("H15 R15 K15 J15")), - Subsignal("ad0_n", Pins("E16")), - Subsignal("ad0_p", Pins("F16")), - Subsignal("ad8_n", Pins("D17")), - Subsignal("ad8_p", Pins("D16")), - IOStandard("LVCMOS18")), - - ("fmc_clocks", 0, - Subsignal("clk0_n", Pins("L19")), - Subsignal("clk0_p", Pins("L18")), - Subsignal("clk1_n", Pins("C19")), - Subsignal("clk1_p", Pins("D18")), - IOStandard("LVCMOS18")), - - ("fmc", 0, - Subsignal("scl", Pins("R7")), - Subsignal("sda", Pins("U7")), - - Subsignal("prsnt", Pins("AB14")), - - # 0, 1, 17, 18 can be clock signals - Subsignal("la_n", Pins( - "M20 N20 P18 P22 M22 K18 L22 T17 " - "J22 R21 T19 N18 P21 M17 K20 J17 " - "K21 B20 C20 G16 G21 E20 F19 D15 " - "A19 C22 E18 D21 A17 C18 B15 B17 " - "A22 B22")), - Subsignal("la_p", Pins( - "M19 N19 P17 N22 M21 J18 L21 T16 " - "J21 R20 R19 N17 P20 L17 K19 J16 " - "J20 B19 D20 G15 G20 E19 G19 E15 " - "A18 D22 F18 E21 A16 C17 C15 B16 " - "A21 B21")), - IOStandard("LVCMOS18")), -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk100" - default_clk_period = 10 - - def __init__(self): - XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io) diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py deleted file mode 100644 index 238d64dd..00000000 --- a/mibuild/platforms/ztex_115d.py +++ /dev/null @@ -1,109 +0,0 @@ -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform - -_io = [ - ("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")), - ("clk_if", 0, Pins("K20"), IOStandard("LVCMOS33")), - ("rst", 0, Pins("A18")), - # PROG_B and DONE: AA1 U16 - - ("fx2", 0, - Subsignal("sloe", Pins("U15"), Drive(12)), # M1 - Subsignal("slrd", Pins("N22"), Drive(12)), - Subsignal("slwr", Pins("M22"), Drive(12)), - Subsignal("pktend", Pins("AB5"), Drive(12)), # CSO - Subsignal("fifoadr", Pins("W17 Y18"), Drive(12)), # CCLK M0 - Subsignal("cont", Pins("G20")), - Subsignal("fd", Pins("Y17 V13 W13 AA8 AB8 W6 Y6 Y9 " - "V21 V22 U20 U22 R20 R22 P18 P19")), - Subsignal("flag", Pins("F20 F19 F18 AB17")), # - - - CSI/MOSI - Subsignal("rdy25", Pins("M21 K21 K22 J21")), - Subsignal("ctl35", Pins("D19 E20 N20")), - Subsignal("int45", Pins("C18 V17")), - Subsignal("pc", Pins("G20 T10 V5 AB9 G19 H20 H19 H18")), - # - DOUT/BUSY INIT_B RDWR_B DO CS CLK DI - IOStandard("LVCMOS33")), - - ("mm", 0, - Subsignal("a", Pins("M20 M19 M18 N19 T19 T21 T22 R19 ", - "P20 P21 P22 J22 H21 H22 G22 F21")), - Subsignal("d", Pins("D20 C20 C19 B21 B20 J19 K19 L19"), Drive(2)), - Subsignal("wr_n", Pins("C22")), - Subsignal("rd_n", Pins("D21")), - Subsignal("psen_n", Pins("D22")), - IOStandard("LVCMOS33")), - - ("serial", 0, - Subsignal("tx", Pins("B22"), Misc("SLEW=QUIETIO")), - Subsignal("rx", Pins("A21"), Misc("PULLDOWN")), - IOStandard("LVCMOS33")), - - ("ddram_clock", 0, - Subsignal("p", Pins("F2"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("n", Pins("F1"), Misc("OUT_TERM=UNTUNED_50")), - IOStandard("SSTL18_II")), - - ("ddram", 0, - Subsignal("dqs", Pins("L3 T2"), IOStandard("SSTL18_II"), # DIFF_ - Misc("IN_TERM=NONE")), - Subsignal("dqs_n", Pins("L1 T1"), IOStandard("SSTL18_II"), # DIFF_ - Misc("IN_TERM=NONE")), - Subsignal("dm", Pins("H1 H2"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("dq", Pins("M1 M2 J1 K2 J3 K1 N3 N1 " - "U1 U3 P1 R3 P2 R1 V2 V1"), Misc("IN_TERM=NONE")), - Subsignal("ras_n", Pins("N4"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("cas_n", Pins("P3"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("a", Pins("M5 K6 B1 J4 L4 K3 M4 K5 G3 G1 K4 C3 C1"), - Misc("OUT_TERM=UNTUNED_50")), - Subsignal("ba", Pins("E3 E1 D1"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("cke", Pins("J6"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("cs_n", Pins("H6")), # NC! - Subsignal("odt", Pins("M3"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("we_n", Pins("D2")), - Subsignal("rzq", Pins("AA2")), - Subsignal("zio", Pins("Y2")), - IOStandard("SSTL18_II")), - - ("i2c", 0, - Subsignal("scl", Pins("F22")), - Subsignal("sda", Pins("E22")), - IOStandard("LVCMOS33")), - - ("sd", 0, - Subsignal("sck", Pins("H11")), - Subsignal("d3", Pins("H14")), - Subsignal("d", Pins("P10")), - Subsignal("d1", Pins("T18")), - Subsignal("d2", Pins("R17")), - Subsignal("cmd", Pins("H13")), - IOStandard("LVCMOS33")), - -] - - -class Platform(XilinxPlatform): - default_clk_name = "clk_if" - default_clk_period = 20 - - def __init__(self): - XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io) - self.add_platform_command(""" -CONFIG VCCAUX = "2.5"; -""") - - def do_finalize(self, fragment): - XilinxPlatform.do_finalize(self, fragment) - - try: - clk_if = self.lookup_request("clk_if") - clk_fx = self.lookup_request("clk_fx") - self.add_platform_command(""" -NET "{clk_if}" TNM_NET = "GRPclk_if"; -NET "{clk_fx}" TNM_NET = "GRPclk_fx"; -TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%; -TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%; -TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY; -TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY; -""", clk_if=clk_if, clk_fx=clk_fx) - except ConstraintError: - pass diff --git a/mibuild/sim/__init__.py b/mibuild/sim/__init__.py deleted file mode 100644 index 439f0a8e..00000000 --- a/mibuild/sim/__init__.py +++ /dev/null @@ -1 +0,0 @@ -from mibuild.sim.platform import SimPlatform diff --git a/mibuild/sim/common.py b/mibuild/sim/common.py deleted file mode 100644 index 38741fd4..00000000 --- a/mibuild/sim/common.py +++ /dev/null @@ -1 +0,0 @@ -sim_special_overrides = {} diff --git a/mibuild/sim/dut_tb.cpp b/mibuild/sim/dut_tb.cpp deleted file mode 100644 index 0e8dac7e..00000000 --- a/mibuild/sim/dut_tb.cpp +++ /dev/null @@ -1,399 +0,0 @@ -// This file is Copyright (c) 2015 Florent Kermarrec -// License: BSD -#include "Vdut.h" -#include "verilated.h" -#include "verilated_vcd_c.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* ios */ - -#ifdef SERIAL_SOURCE_STB -#define WITH_SERIAL -#endif - -#ifdef ETH_SOURCE_STB -#define WITH_ETH -#endif - -#define MAX(a,b) (((a)>(b))?(a):(b)) -#define MIN(a,b) (((a)<(b))?(a):(b)) - -int trace = 0; - -vluint64_t main_time = 0; -double sc_time_stamp() -{ - return main_time; -} - -/* Sim struct */ -struct sim { - bool run; - - unsigned int tick; - clock_t start; - clock_t end; - float speed; - -#ifdef WITH_SERIAL_PTY - char serial_dev[64]; - int serial_fd; - unsigned char serial_rx_data; - unsigned char serial_tx_data; -#endif -#ifdef WITH_ETH - const char *eth_dev; - const char *eth_tap; - int eth_fd; - unsigned char eth_txbuffer[2048]; - unsigned char eth_rxbuffer[2048]; - int eth_txbuffer_len; - int eth_rxbuffer_len; - int eth_rxbuffer_pos; - int eth_last_source_stb; -#endif -}; - -/* Serial functions */ -#ifndef WITH_SERIAL_PTY -struct termios orig_termios; - -void reset_terminal_mode(void) -{ - tcsetattr(0, TCSANOW, &orig_termios); -} - -void set_conio_terminal_mode(void) -{ - struct termios new_termios; - - /* take two copies - one for now, one for later */ - tcgetattr(0, &orig_termios); - memcpy(&new_termios, &orig_termios, sizeof(new_termios)); - - /* register cleanup handler, and set the new terminal mode */ - atexit(reset_terminal_mode); - cfmakeraw(&new_termios); - tcsetattr(0, TCSANOW, &new_termios); -} - -int kbhit(void) -{ - struct timeval tv = { 0L, 0L }; - fd_set fds; - FD_ZERO(&fds); - FD_SET(0, &fds); - return select(1, &fds, NULL, NULL, &tv); -} - -int getch(void) -{ - int r; - unsigned char c; - if((r = read(0, &c, sizeof(c))) < 0) { - return r; - } else { - return c; - } -} -#endif - -/* Ethernet functions */ -/* create tap: - openvpn --mktun --dev tap0 - ifconfig tap0 192.168.0.14 up - mknod /dev/net/tap0 c 10 200 - delete tap: - openvpn --rmtun --dev tap0 */ -#ifdef WITH_ETH -void eth_init(struct sim *s, const char *dev, const char*tap) -{ - s->eth_txbuffer_len = 0; - s->eth_rxbuffer_len = 0; - s->eth_rxbuffer_pos = 0; - s->eth_last_source_stb = 0; - s->eth_dev = dev; - s->eth_tap = tap; -} - -void eth_open(struct sim *s) -{ - - struct ifreq ifr; - s->eth_fd = open (s->eth_dev, O_RDWR); - if(s->eth_fd < 0) { - fprintf(stderr, " Could not open dev %s\n", s->eth_dev); - return; - } - - memset(&ifr, 0, sizeof(ifr)); - ifr.ifr_flags = IFF_TAP | IFF_NO_PI; - strncpy(ifr.ifr_name, s->eth_tap, IFNAMSIZ); - - if(ioctl(s->eth_fd, TUNSETIFF, (void *) &ifr) < 0) { - fprintf(stderr, " Could not set %s\n", s->eth_tap); - close(s->eth_fd); - } - return; -} - -int eth_close(struct sim *s) -{ - if(s->eth_fd < 0) - close(s->eth_fd); -} - -void eth_write(struct sim *s, unsigned char *buf, int len) -{ - write(s->eth_fd, buf, len); -} - -int eth_read(struct sim *s, unsigned char *buf) -{ - - struct pollfd fds[1]; - int n; - int len; - - fds[0].fd = s->eth_fd; - fds[0].events = POLLIN; - - n = poll(fds, 1, 0); - if((n > 0) && ((fds[0].revents & POLLIN) == POLLIN)) { - len = read(s->eth_fd, buf, 1532); - } else { - len = 0; - } - return len; -} -#endif - -Vdut* dut; -VerilatedVcdC* tfp; - -#ifndef WITH_SERIAL_PTY -int console_service(struct sim *s) -{ - /* fpga --> console */ - SERIAL_SOURCE_ACK = 1; - if(SERIAL_SOURCE_STB == 1) { - if(SERIAL_SOURCE_DATA == '\n') - putchar('\r'); - putchar(SERIAL_SOURCE_DATA); - fflush(stdout); - } - - /* console --> fpga */ - SERIAL_SINK_STB = 0; - if(s->tick%(1000) == 0) { - if(kbhit()) { - char c = getch(); - if(c == 27 && !kbhit()) { - printf("\r\n"); - return -1; - } else { - SERIAL_SINK_STB = 1; - SERIAL_SINK_DATA = c; - } - } - } - return 0; -} -#else -void console_init(struct sim *s) -{ - FILE *f; - f = fopen("/tmp/simserial","r"); - fscanf(f, "%[^\n]", s->serial_dev); - fclose(f); - return; -} - -void console_open(struct sim *s) -{ - s->serial_fd = open(s->serial_dev, O_RDWR); - if(s->serial_fd < 0) { - fprintf(stderr, " Could not open dev %s\n", s->serial_dev); - return; - } - return; -} - -int console_close(struct sim *s) -{ - if(s->serial_fd < 0) - close(s->serial_fd); -} - -void console_write(struct sim *s, unsigned char *buf, int len) -{ - write(s->serial_fd, buf, len); -} - -int console_read(struct sim *s, unsigned char *buf) -{ - struct pollfd fds[1]; - int n; - int len; - - fds[0].fd = s->serial_fd; - fds[0].events = POLLIN; - - n = poll(fds, 1, 0); - if((n > 0) && ((fds[0].revents & POLLIN) == POLLIN)) { - len = read(s->serial_fd, buf, 1); - } else { - len = 0; - } - return len; -} - -int console_service(struct sim *s) -{ - /* fpga --> console */ - SERIAL_SOURCE_ACK = 1; - if(SERIAL_SOURCE_STB == 1) { - s->serial_tx_data = SERIAL_SOURCE_DATA; - console_write(s, &(s->serial_tx_data), 1); - } - - /* console --> fpga */ - SERIAL_SINK_STB = 0; - if(console_read(s, &(s->serial_rx_data))) - { - SERIAL_SINK_STB = 1; - SERIAL_SINK_DATA = s->serial_rx_data; - } - return 0; -} -#endif - -#ifdef WITH_ETH -int ethernet_service(struct sim *s) { - /* fpga --> tap */ - ETH_SOURCE_ACK = 1; - if(ETH_SOURCE_STB == 1) { - s->eth_txbuffer[s->eth_txbuffer_len] = ETH_SOURCE_DATA; - s->eth_txbuffer_len++; - } else { - if(s->eth_last_source_stb) { - eth_write(s, s->eth_txbuffer, s->eth_txbuffer_len); - s->eth_txbuffer_len = 0; - } - } - s->eth_last_source_stb = ETH_SOURCE_STB; - - /* tap --> fpga */ - if(s->eth_rxbuffer_len == 0) { - ETH_SINK_STB = 0; - s->eth_rxbuffer_pos = 0; - s->eth_rxbuffer_len = eth_read(s, s->eth_rxbuffer); - } else { - if(s->eth_rxbuffer_pos < MAX(s->eth_rxbuffer_len, 60)) { - ETH_SINK_STB = 1; - ETH_SINK_DATA = s->eth_rxbuffer[s->eth_rxbuffer_pos]; - s->eth_rxbuffer_pos++; - } else { - ETH_SINK_STB = 0; - s->eth_rxbuffer_len = 0; - memset(s->eth_rxbuffer, 0, 1532); - } - } -} -#endif - -void sim_tick(struct sim *s) -{ - SYS_CLK = s->tick%2; - dut->eval(); - if(trace) - tfp->dump(s->tick); - s->tick++; -} - -void sim_init(struct sim *s) -{ - int i; - s->tick = 0; -#ifdef SYS_RST - SYS_RST = 1; - SYS_CLK = 0; - for (i=0; i<8; i++) - sim_tick(s); - SYS_RST = 0; -#endif - s->start = clock(); -} - -int main(int argc, char **argv, char **env) -{ - float speed; - -#ifndef WITH_SERIAL_PTY - set_conio_terminal_mode(); -#endif - - Verilated::commandArgs(argc, argv); - dut = new Vdut; - - Verilated::traceEverOn(true); - tfp = new VerilatedVcdC; - dut->trace(tfp, 99); - tfp->open("dut.vcd"); - - struct sim s; - sim_init(&s); - -#ifdef WITH_SERIAL_PTY - console_init(&s); - console_open(&s); -#endif - -#ifdef WITH_ETH - eth_init(&s, "/dev/net/tap0", "tap0"); // XXX get this from /tmp/simethernet - eth_open(&s); -#endif - - s.run = true; - while(s.run) { - sim_tick(&s); - if(SYS_CLK) { -#ifdef WITH_SERIAL - if(console_service(&s) != 0) - s.run = false; -#endif -#ifdef WITH_ETH - ethernet_service(&s); -#endif - } - } - s.end = clock(); - - speed = (s.tick/2)/((s.end-s.start)/CLOCKS_PER_SEC); - - printf("average speed: %3.3f MHz\n\r", speed/1000000); - - tfp->close(); - - -#ifdef WITH_SERIAL_PTY - console_close(&s); -#endif -#ifdef WITH_ETH - eth_close(&s); -#endif - - exit(0); -} diff --git a/mibuild/sim/platform.py b/mibuild/sim/platform.py deleted file mode 100644 index c36cef04..00000000 --- a/mibuild/sim/platform.py +++ /dev/null @@ -1,20 +0,0 @@ -from mibuild.generic_platform import GenericPlatform -from mibuild.sim import common, verilator - - -class SimPlatform(GenericPlatform): - def __init__(self, *args, toolchain="verilator", **kwargs): - GenericPlatform.__init__(self, *args, **kwargs) - if toolchain == "verilator": - self.toolchain = verilator.SimVerilatorToolchain() - else: - raise ValueError("Unknown toolchain") - - def get_verilog(self, *args, special_overrides=dict(), **kwargs): - so = dict(common.sim_special_overrides) - so.update(special_overrides) - return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) - - def build(self, *args, **kwargs): - return self.toolchain.build(self, *args, **kwargs) - diff --git a/mibuild/sim/verilator.py b/mibuild/sim/verilator.py deleted file mode 100644 index 1bc68791..00000000 --- a/mibuild/sim/verilator.py +++ /dev/null @@ -1,152 +0,0 @@ -# This file is Copyright (c) 2015 Florent Kermarrec -# License: BSD - -import os -import subprocess - -from migen.fhdl.std import * -from migen.fhdl.structure import _Fragment -from mibuild.generic_platform import * - -from mibuild import tools -from mibuild.sim import common - - -def _build_tb(platform, vns, serial, template): - - def io_name(ressource, subsignal=None): - res = platform.lookup_request(ressource) - if subsignal is not None: - res = getattr(res, subsignal) - return vns.get_name(res) - - ios = """ -#define SYS_CLK dut->{sys_clk} -""".format(sys_clk=io_name("sys_clk")) - - if serial == "pty": - ios += "#define WITH_SERIAL_PTY" - elif serial == "console": - pass - else: - raise ValueError - try: - ios += """ -#define SERIAL_SOURCE_STB dut->{serial_source_stb} -#define SERIAL_SOURCE_ACK dut->{serial_source_ack} -#define SERIAL_SOURCE_DATA dut->{serial_source_data} - -#define SERIAL_SINK_STB dut->{serial_sink_stb} -#define SERIAL_SINK_ACK dut->{serial_sink_ack} -#define SERIAL_SINK_DATA dut->{serial_sink_data} -""".format( - serial_source_stb=io_name("serial", "source_stb"), - serial_source_ack=io_name("serial", "source_ack"), - serial_source_data=io_name("serial", "source_data"), - - serial_sink_stb=io_name("serial", "sink_stb"), - serial_sink_ack=io_name("serial", "sink_ack"), - serial_sink_data=io_name("serial", "sink_data"), - ) - except: - pass - - try: - ios += """ -#define ETH_SOURCE_STB dut->{eth_source_stb} -#define ETH_SOURCE_ACK dut->{eth_source_ack} -#define ETH_SOURCE_DATA dut->{eth_source_data} - -#define ETH_SINK_STB dut->{eth_sink_stb} -#define ETH_SINK_ACK dut->{eth_sink_ack} -#define ETH_SINK_DATA dut->{eth_sink_data} -""".format( - eth_source_stb=io_name("eth", "source_stb"), - eth_source_ack=io_name("eth", "source_ack"), - eth_source_data=io_name("eth", "source_data"), - - eth_sink_stb=io_name("eth", "sink_stb"), - eth_sink_ack=io_name("eth", "sink_ack"), - eth_sink_data=io_name("eth", "sink_data"), - ) - except: - pass - - content = "" - f = open(template, "r") - done = False - for l in f: - content += l - if "/* ios */" in l and not done: - content += ios - done = True - - f.close() - tools.write_to_file("dut_tb.cpp", content) - - -def _build_sim(platform, vns, build_name, include_paths, sim_path, serial, verbose): - include = "" - for path in include_paths: - include += "-I"+path+" " - - build_script_contents = """# Autogenerated by mibuild - rm -rf obj_dir/ -verilator {disable_warnings} -O3 --cc dut.v --exe dut_tb.cpp -LDFLAGS "-lpthread" -trace {include} -make -j -C obj_dir/ -f Vdut.mk Vdut - -""".format( - disable_warnings="-Wno-fatal", - include=include) - build_script_file = "build_" + build_name + ".sh" - tools.write_to_file(build_script_file, build_script_contents, force_unix=True) - - _build_tb(platform, vns, serial, os.path.join("..", sim_path, "dut_tb.cpp")) - if verbose: - r = subprocess.call(["bash", build_script_file]) - else: - r = subprocess.call(["bash", build_script_file], stdout=subprocess.DEVNULL, stderr=subprocess.STDOUT) - if r != 0: - raise OSError("Subprocess failed") - - -def _run_sim(build_name): - run_script_contents = """obj_dir/Vdut -""" - run_script_file = "run_" + build_name + ".sh" - tools.write_to_file(run_script_file, run_script_contents, force_unix=True) - r = subprocess.call(["bash", run_script_file]) - if r != 0: - raise OSError("Subprocess failed") - - -class SimVerilatorToolchain: - # XXX fir sim_path - def build(self, platform, fragment, build_dir="build", build_name="top", - sim_path="../migen/mibuild/sim/", serial="console", - run=True, verbose=False): - tools.mkdir_noerror(build_dir) - os.chdir(build_dir) - - if not isinstance(fragment, _Fragment): - fragment = fragment.get_fragment() - platform.finalize(fragment) - - v_output = platform.get_verilog(fragment) - named_sc, named_pc = platform.resolve_signals(v_output.ns) - v_output.write("dut.v") - - include_paths = [] - for source in platform.sources: - path = os.path.dirname(source[0]).replace("\\", "\/") - if path not in include_paths: - include_paths.append(path) - include_paths += platform.verilog_include_paths - _build_sim(platform, v_output.ns, build_name, include_paths, sim_path, serial, verbose) - - if run: - _run_sim(build_name) - - os.chdir("..") - - return v_output.ns diff --git a/mibuild/tools.py b/mibuild/tools.py deleted file mode 100644 index 9e0880d5..00000000 --- a/mibuild/tools.py +++ /dev/null @@ -1,42 +0,0 @@ -import os -import struct -from distutils.version import StrictVersion - - -def mkdir_noerror(d): - try: - os.mkdir(d) - except OSError: - pass - - -def language_by_filename(name): - extension = name.rsplit(".")[-1] - if extension in ["v", "vh", "vo"]: - return "verilog" - if extension in ["vhd", "vhdl", "vho"]: - return "vhdl" - return None - - -def write_to_file(filename, contents, force_unix=False): - newline = None - if force_unix: - newline = "\n" - with open(filename, "w", newline=newline) as f: - f.write(contents) - - -def arch_bits(): - return struct.calcsize("P")*8 - - -def versions(path): - for n in os.listdir(path): - full = os.path.join(path, n) - if not os.path.isdir(full): - continue - try: - yield StrictVersion(n) - except ValueError: - continue diff --git a/mibuild/xilinx/__init__.py b/mibuild/xilinx/__init__.py deleted file mode 100644 index 0594435c..00000000 --- a/mibuild/xilinx/__init__.py +++ /dev/null @@ -1,2 +0,0 @@ -from mibuild.xilinx.platform import XilinxPlatform -from mibuild.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept diff --git a/mibuild/xilinx/common.py b/mibuild/xilinx/common.py deleted file mode 100644 index ba125659..00000000 --- a/mibuild/xilinx/common.py +++ /dev/null @@ -1,147 +0,0 @@ -import os -import sys -from distutils.version import StrictVersion - -from migen.fhdl.std import * -from migen.fhdl.specials import SynthesisDirective -from migen.genlib.cdc import * -from migen.genlib.resetsync import AsyncResetSynchronizer -from migen.genlib.io import * -from mibuild import tools - - -def settings(path, ver=None, sub=None): - vers = list(tools.versions(path)) - if ver is None: - ver = max(vers) - else: - ver = StrictVersion(ver) - assert ver in vers - - full = os.path.join(path, str(ver)) - if sub: - full = os.path.join(full, sub) - - search = [64, 32] - if tools.arch_bits() == 32: - search.reverse() - - if sys.platform == "win32" or sys.platform == "cygwin": - script_ext = "bat" - else: - script_ext = "sh" - - for b in search: - settings = os.path.join(full, "settings{0}.{1}".format(b, script_ext)) - if os.path.exists(settings): - return settings - - raise OSError("no settings file found") - - -class XilinxNoRetimingImpl(Module): - def __init__(self, reg): - self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg) - - -class XilinxNoRetiming: - @staticmethod - def lower(dr): - return XilinxNoRetimingImpl(dr.reg) - - -class XilinxMultiRegImpl(MultiRegImpl): - def __init__(self, *args, **kwargs): - MultiRegImpl.__init__(self, *args, **kwargs) - self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r) - for r in self.regs] - - -class XilinxMultiReg: - @staticmethod - def lower(dr): - return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n) - - -class XilinxAsyncResetSynchronizerImpl(Module): - def __init__(self, cd, async_reset): - rst1 = Signal() - self.specials += [ - Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset, - i_CE=1, i_C=cd.clk, o_Q=rst1), - Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset, - i_CE=1, i_C=cd.clk, o_Q=cd.rst) - ] - - -class XilinxAsyncResetSynchronizer: - @staticmethod - def lower(dr): - return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) - - -class XilinxDifferentialInputImpl(Module): - def __init__(self, i_p, i_n, o): - self.specials += Instance("IBUFDS", i_I=i_p, i_IB=i_n, o_O=o) - - -class XilinxDifferentialInput: - @staticmethod - def lower(dr): - return XilinxDifferentialInputImpl(dr.i_p, dr.i_n, dr.o) - - -class XilinxDifferentialOutputImpl(Module): - def __init__(self, i, o_p, o_n): - self.specials += Instance("OBUFDS", i_I=i, o_O=o_p, o_OB=o_n) - - -class XilinxDifferentialOutput: - @staticmethod - def lower(dr): - return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) - - -class XilinxDDROutputImpl(Module): - def __init__(self, i1, i2, o, clk): - self.specials += Instance("ODDR2", - p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC", - i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0, - i_D0=i1, i_D1=i2, o_Q=o, - ) - - -class XilinxDDROutput: - @staticmethod - def lower(dr): - return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) - - -xilinx_special_overrides = { - NoRetiming: XilinxNoRetiming, - MultiReg: XilinxMultiReg, - AsyncResetSynchronizer: XilinxAsyncResetSynchronizer, - DifferentialInput: XilinxDifferentialInput, - DifferentialOutput: XilinxDifferentialOutput, - DDROutput: XilinxDDROutput -} - - -class XilinxDDROutputImplS7(Module): - def __init__(self, i1, i2, o, clk): - self.specials += Instance("ODDR", - p_DDR_CLK_EDGE="SAME_EDGE", - i_C=clk, i_CE=1, i_S=0, i_R=0, - i_D1=i1, i_D2=i2, o_Q=o, - ) - - -class XilinxDDROutputS7: - @staticmethod - def lower(dr): - return XilinxDDROutputImplS7(dr.i1, dr.i2, dr.o, dr.clk) - - -xilinx_s7_special_overrides = { - DDROutput: XilinxDDROutputS7 -} diff --git a/mibuild/xilinx/ise.py b/mibuild/xilinx/ise.py deleted file mode 100644 index 92f37517..00000000 --- a/mibuild/xilinx/ise.py +++ /dev/null @@ -1,205 +0,0 @@ -import os -import subprocess -import sys - -from migen.fhdl.std import * -from migen.fhdl.structure import _Fragment - -from mibuild.generic_platform import * -from mibuild import tools -from mibuild.xilinx import common - - -def _format_constraint(c): - if isinstance(c, Pins): - return "LOC=" + c.identifiers[0] - elif isinstance(c, IOStandard): - return "IOSTANDARD=" + c.name - elif isinstance(c, Drive): - return "DRIVE=" + str(c.strength) - elif isinstance(c, Misc): - return c.misc - - -def _format_ucf(signame, pin, others, resname): - fmt_c = [] - for c in [Pins(pin)] + others: - fc = _format_constraint(c) - if fc is not None: - fmt_c.append(fc) - fmt_r = resname[0] + ":" + str(resname[1]) - if resname[2] is not None: - fmt_r += "." + resname[2] - return "NET \"" + signame + "\" " + " | ".join(fmt_c) + "; # " + fmt_r + "\n" - - -def _build_ucf(named_sc, named_pc): - r = "" - for sig, pins, others, resname in named_sc: - if len(pins) > 1: - for i, p in enumerate(pins): - r += _format_ucf(sig + "(" + str(i) + ")", p, others, resname) - else: - r += _format_ucf(sig, pins[0], others, resname) - if named_pc: - r += "\n" + "\n\n".join(named_pc) - return r - - -def _build_xst_files(device, sources, vincpaths, build_name, xst_opt): - prj_contents = "" - for filename, language, library in sources: - prj_contents += language + " " + library + " " + filename + "\n" - tools.write_to_file(build_name + ".prj", prj_contents) - - xst_contents = """run --ifn {build_name}.prj --top top -{xst_opt} --ofn {build_name}.ngc --p {device} -""".format(build_name=build_name, xst_opt=xst_opt, device=device) - for path in vincpaths: - xst_contents += "-vlgincdir " + path + "\n" - tools.write_to_file(build_name + ".xst", xst_contents) - - -def _run_yosys(device, sources, vincpaths, build_name): - ys_contents = "" - incflags = "" - for path in vincpaths: - incflags += " -I" + path - for filename, language, library in sources: - ys_contents += "read_{}{} {}\n".format(language, incflags, filename) - - ys_contents += """hierarchy -check -top top -proc; memory; opt; fsm; opt -synth_xilinx -top top -edif {build_name}.edif""".format(build_name=build_name) - - ys_name = build_name + ".ys" - tools.write_to_file(ys_name, ys_contents) - r = subprocess.call(["yosys", ys_name]) - if r != 0: - raise OSError("Subprocess failed") - - -def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt, - bitgen_opt, ise_commands, map_opt, par_opt, ver=None): - if sys.platform == "win32" or sys.platform == "cygwin": - source_cmd = "call " - script_ext = ".bat" - shell = ["cmd", "/c"] - build_script_contents = "@echo off\nrem Autogenerated by mibuild\n" - else: - source_cmd = "source " - script_ext = ".sh" - shell = ["bash"] - build_script_contents = "# Autogenerated by mibuild\nset -e\n" - if source: - settings = common.settings(ise_path, ver, "ISE_DS") - build_script_contents += source_cmd + settings + "\n" - if mode == "edif": - ext = "edif" - else: - ext = "ngc" - build_script_contents += """ -xst -ifn {build_name}.xst -""" - - build_script_contents += """ -ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd -map {map_opt} -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf -par {par_opt} {build_name}_map.ncd {build_name}.ncd {build_name}.pcf -bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit -""" - build_script_contents = build_script_contents.format(build_name=build_name, - ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext, - par_opt=par_opt, map_opt=map_opt) - build_script_contents += ise_commands.format(build_name=build_name) - build_script_file = "build_" + build_name + script_ext - tools.write_to_file(build_script_file, build_script_contents, force_unix=False) - command = shell + [build_script_file] - r = subprocess.call(command) - if r != 0: - raise OSError("Subprocess failed") - - -def _default_ise_path(): - if sys.platform == "win32": - return "C:\\Xilinx" - elif sys.platform == "cygwin": - return "/cygdrive/c/Xilinx" - else: - return "/opt/Xilinx" - - -def _default_source(): - return False if sys.platform == "win32" else True - - -class XilinxISEToolchain: - def __init__(self): - self.xst_opt = """-ifmt MIXED --use_new_parser yes --opt_mode SPEED --register_balancing yes""" - self.map_opt = "-ol high -w" - self.par_opt = "-ol high -w" - self.ngdbuild_opt = "" - self.bitgen_opt = "-g Binary:Yes -w" - self.ise_commands = "" - - def build(self, platform, fragment, build_dir="build", build_name="top", - ise_path=_default_ise_path(), source=_default_source(), run=True, mode="xst"): - if not isinstance(fragment, _Fragment): - fragment = fragment.get_fragment() - platform.finalize(fragment) - - ngdbuild_opt = self.ngdbuild_opt - - vns = None - - tools.mkdir_noerror(build_dir) - cwd = os.getcwd() - os.chdir(build_dir) - try: - if mode == "xst" or mode == "yosys": - v_output = platform.get_verilog(fragment) - vns = v_output.ns - named_sc, named_pc = platform.resolve_signals(vns) - v_file = build_name + ".v" - v_output.write(v_file) - sources = platform.sources | {(v_file, "verilog", "work")} - if mode == "xst": - _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt) - isemode = "xst" - else: - _run_yosys(platform.device, sources, platform.verilog_include_paths, build_name) - isemode = "edif" - ngdbuild_opt += "-p " + platform.device - - if mode == "mist": - from mist import synthesize - synthesize(fragment, platform.constraint_manager.get_io_signals()) - - if mode == "edif" or mode == "mist": - e_output = platform.get_edif(fragment) - vns = e_output.ns - named_sc, named_pc = platform.resolve_signals(vns) - e_file = build_name + ".edif" - e_output.write(e_file) - isemode = "edif" - - tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) - if run: - _run_ise(build_name, ise_path, source, isemode, - ngdbuild_opt, self.bitgen_opt, self.ise_commands, - self.map_opt, self.par_opt) - finally: - os.chdir(cwd) - - return vns - - def add_period_constraint(self, platform, clk, period): - platform.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}"; -TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk) diff --git a/mibuild/xilinx/platform.py b/mibuild/xilinx/platform.py deleted file mode 100644 index 201ad53a..00000000 --- a/mibuild/xilinx/platform.py +++ /dev/null @@ -1,33 +0,0 @@ -from mibuild.generic_platform import GenericPlatform -from mibuild.xilinx import common, vivado, ise - - -class XilinxPlatform(GenericPlatform): - bitstream_ext = ".bit" - - def __init__(self, *args, toolchain="ise", **kwargs): - GenericPlatform.__init__(self, *args, **kwargs) - if toolchain == "ise": - self.toolchain = ise.XilinxISEToolchain() - elif toolchain == "vivado": - self.toolchain = vivado.XilinxVivadoToolchain() - else: - raise ValueError("Unknown toolchain") - - def get_verilog(self, *args, special_overrides=dict(), **kwargs): - so = dict(common.xilinx_special_overrides) - if self.device[:3] == "xc7": - so.update(dict(common.xilinx_s7_special_overrides)) - so.update(special_overrides) - return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) - - def get_edif(self, fragment, **kwargs): - return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs) - - def build(self, *args, **kwargs): - return self.toolchain.build(self, *args, **kwargs) - - def add_period_constraint(self, clk, period): - if hasattr(clk, "p"): - clk = clk.p - self.toolchain.add_period_constraint(self, clk, period) diff --git a/mibuild/xilinx/programmer.py b/mibuild/xilinx/programmer.py deleted file mode 100644 index ce7ca8a5..00000000 --- a/mibuild/xilinx/programmer.py +++ /dev/null @@ -1,199 +0,0 @@ -import os -import sys -import subprocess - -from mibuild.generic_programmer import GenericProgrammer -from mibuild.xilinx import common - - -def _run_urjtag(cmds): - with subprocess.Popen("jtag", stdin=subprocess.PIPE) as process: - process.stdin.write(cmds.encode("ASCII")) - process.communicate() - - -class UrJTAG(GenericProgrammer): - needs_bitreverse = True - - def __init__(self, cable, flash_proxy_basename=None): - GenericProgrammer.__init__(self, flash_proxy_basename) - self.cable = cable - - def load_bitstream(self, bitstream_file): - cmds = """cable {cable} -detect -pld load {bitstream} -quit -""".format(bitstream=bitstream_file, cable=self.cable) - _run_urjtag(cmds) - - def flash(self, address, data_file): - flash_proxy = self.find_flash_proxy() - cmds = """cable {cable} -detect -pld load "{flash_proxy}" -initbus fjmem opcode=000010 -frequency 6000000 -detectflash 0 -endian big -flashmem "{address}" "{data_file}" noverify -""".format(flash_proxy=flash_proxy, address=address, data_file=data_file, - cable=self.cable) - _run_urjtag(cmds) - - -class XC3SProg(GenericProgrammer): - needs_bitreverse = False - - def __init__(self, cable, flash_proxy_basename=None): - GenericProgrammer.__init__(self, flash_proxy_basename) - self.cable = cable - - def load_bitstream(self, bitstream_file): - subprocess.call(["xc3sprog", "-v", "-c", self.cable, bitstream_file]) - - def flash(self, address, data_file): - flash_proxy = self.find_flash_proxy() - subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)]) - - - -class FpgaProg(GenericProgrammer): - needs_bitreverse = False - - def __init__(self, flash_proxy_basename=None): - GenericProgrammer.__init__(self, flash_proxy_basename) - - def load_bitstream(self, bitstream_file): - subprocess.call(["fpgaprog", "-v", "-f", bitstream_file]) - - def flash(self, address, data_file): - if address != 0: - raise ValueError("fpga prog needs a main bitstream at address 0") - flash_proxy = self.find_flash_proxy() - subprocess.call(["fpgaprog", "-v", "-sa", "-r", "-b", flash_proxy, - "-f", data_file]) - - -def _run_impact(cmds): - with subprocess.Popen("impact -batch", stdin=subprocess.PIPE, shell=True) as process: - process.stdin.write(cmds.encode("ASCII")) - process.communicate() - return process.returncode - - -def _create_xsvf(bitstream_file, xsvf_file): - assert os.path.exists(bitstream_file), bitstream_file - assert not os.path.exists(xsvf_file), xsvf_file - assert 0 == _run_impact(""" -setPreference -pref KeepSVF:True -setMode -bs -setCable -port xsvf -file {xsvf} -addDevice -p 1 -file {bitstream} -program -p 1 -quit -""".format(bitstream=bitstream_file, xsvf=xsvf_file)) - - -class iMPACT(GenericProgrammer): - needs_bitreverse = False - - def load_bitstream(self, bitstream_file): - cmds = """setMode -bs -setCable -p auto -addDevice -p 1 -file {bitstream} -program -p 1 -quit -""".format(bitstream=bitstream_file) - _run_impact(cmds) - - -def _run_vivado(path, ver, cmds): - if sys.platform == "win32" or sys.platform == "cygwin": - vivado_cmd = "vivado -mode tcl" - else: - settings = common.settings(path, ver) - vivado_cmd = "bash -c \"source " + settings + "&& vivado -mode tcl\"" - with subprocess.Popen(vivado_cmd, stdin=subprocess.PIPE, shell=True) as process: - process.stdin.write(cmds.encode("ASCII")) - process.communicate() - - -class VivadoProgrammer(GenericProgrammer): - needs_bitreverse = False - def __init__(self, vivado_path="/opt/Xilinx/Vivado", vivado_ver=None): - GenericProgrammer.__init__(self) - self.vivado_path = vivado_path - self.vivado_ver = vivado_ver - - def load_bitstream(self, bitstream_file): - cmds = """open_hw -connect_hw_server -open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] - -set_property PROBES.FILE {{}} [lindex [get_hw_devices] 0] -set_property PROGRAM.FILE {{{bitstream}}} [lindex [get_hw_devices] 0] - -program_hw_devices [lindex [get_hw_devices] 0] -refresh_hw_device [lindex [get_hw_devices] 0] - -quit -""".format(bitstream=bitstream_file) - _run_vivado(self.vivado_path, self.vivado_ver, cmds) - - # XXX works to flash bitstream, adapt it to flash bios - def flash(self, address, data_file): - cmds = """open_hw -connect_hw_server -open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] -create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {{n25q256-3.3v-spi-x1_x2_x4}}] 0] - -set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -refresh_hw_device [lindex [get_hw_devices] 0] - -set_property PROGRAM.ADDRESS_RANGE {{use_file}} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.FILES [list "{data}" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] -set_property PROGRAM.UNUSED_PIN_TERMINATION {{pull-none}} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] - -startgroup -if {{![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] }} {{ create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; }}; -program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] -endgroup - -quit -""".format(data=data_file) - _run_vivado(self.vivado_path, self.vivado_ver, cmds) - - -class Adept(GenericProgrammer): - """Using the Adept tool with an onboard Digilent "USB JTAG" cable. - - You need to install Adept Utilities V2 from - http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2 - """ - - needs_bitreverse = False - - def __init__(self, board, index, flash_proxy_basename=None): - GenericProgrammer.__init__(self, flash_proxy_basename) - self.board = board - self.index = index - - def load_bitstream(self, bitstream_file): - subprocess.call([ - "djtgcfg", - "--verbose", - "prog", "-d", self.board, - "-i", str(self.index), - "-f", bitstream_file, - ]) - - def flash(self, address, data_file): - raise ValueError("Flashing unsupported with DigilentAdept tools") diff --git a/mibuild/xilinx/vivado.py b/mibuild/xilinx/vivado.py deleted file mode 100644 index 8f732a49..00000000 --- a/mibuild/xilinx/vivado.py +++ /dev/null @@ -1,138 +0,0 @@ -# This file is Copyright (c) 2014 Florent Kermarrec -# License: BSD - -import os -import subprocess -import sys - -from migen.fhdl.std import * -from migen.fhdl.structure import _Fragment -from mibuild.generic_platform import * - -from mibuild import tools -from mibuild.xilinx import common - - -def _format_constraint(c): - if isinstance(c, Pins): - return "set_property LOC " + c.identifiers[0] - elif isinstance(c, IOStandard): - return "set_property IOSTANDARD " + c.name - elif isinstance(c, Drive): - return "set_property DRIVE " + str(c.strength) - elif isinstance(c, Misc): - return "set_property " + c.misc.replace("=", " ") - else: - raise ValueError("unknown constraint {}".format(c)) - - -def _format_xdc(signame, resname, *constraints): - fmt_c = [_format_constraint(c) for c in constraints] - fmt_r = resname[0] + ":" + str(resname[1]) - if resname[2] is not None: - fmt_r += "." + resname[2] - r = " ## {}\n".format(fmt_r) - for c in fmt_c: - r += c + " [get_ports " + signame + "]\n" - return r - - -def _build_xdc(named_sc, named_pc): - r = "" - for sig, pins, others, resname in named_sc: - if len(pins) > 1: - for i, p in enumerate(pins): - r += _format_xdc(sig + "[" + str(i) + "]", resname, Pins(p), *others) - elif pins: - r += _format_xdc(sig, resname, Pins(pins[0]), *others) - else: - r += _format_xdc(sig, resname, *others) - if named_pc: - r += "\n" + "\n\n".join(named_pc) - return r - - -def _run_vivado(build_name, vivado_path, source, ver=None): - if sys.platform == "win32" or sys.platform == "cygwin": - build_script_contents = "REM Autogenerated by mibuild\n" - build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n" - build_script_file = "build_" + build_name + ".bat" - tools.write_to_file(build_script_file, build_script_contents) - r = subprocess.call([build_script_file]) - else: - build_script_contents = "# Autogenerated by mibuild\nset -e\n" - settings = common.settings(vivado_path, ver) - build_script_contents += "source " + settings + "\n" - build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n" - build_script_file = "build_" + build_name + ".sh" - tools.write_to_file(build_script_file, build_script_contents) - r = subprocess.call(["bash", build_script_file]) - - if r != 0: - raise OSError("Subprocess failed") - - -class XilinxVivadoToolchain: - def __init__(self): - self.bitstream_commands = [] - self.additional_commands = [] - self.pre_synthesis_commands = [] - self.with_phys_opt = False - - def _build_batch(self, platform, sources, build_name): - tcl = [] - for filename, language, library in sources: - tcl.append("add_files " + filename) - tcl.append("set_property library {} [get_files {}]".format(library, filename)) - - tcl.append("read_xdc {}.xdc".format(build_name)) - tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) - tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths))) - tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name)) - tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name)) - tcl.append("place_design") - if self.with_phys_opt: - tcl.append("phys_opt_design -directive AddRetime") - tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name)) - tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name)) - tcl.append("report_io -file {}_io.rpt".format(build_name)) - tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name)) - tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name)) - tcl.append("route_design") - tcl.append("report_route_status -file {}_route_status.rpt".format(build_name)) - tcl.append("report_drc -file {}_drc.rpt".format(build_name)) - tcl.append("report_timing_summary -max_paths 10 -file {}_timing.rpt".format(build_name)) - tcl.append("report_power -file {}_power.rpt".format(build_name)) - for bitstream_command in self.bitstream_commands: - tcl.append(bitstream_command.format(build_name=build_name)) - tcl.append("write_bitstream -force {}.bit ".format(build_name)) - for additional_command in self.additional_commands: - tcl.append(additional_command.format(build_name=build_name)) - tcl.append("quit") - tools.write_to_file(build_name + ".tcl", "\n".join(tcl)) - - def build(self, platform, fragment, build_dir="build", build_name="top", - vivado_path="/opt/Xilinx/Vivado", source=True, run=True): - tools.mkdir_noerror(build_dir) - os.chdir(build_dir) - - if not isinstance(fragment, _Fragment): - fragment = fragment.get_fragment() - platform.finalize(fragment) - v_output = platform.get_verilog(fragment) - named_sc, named_pc = platform.resolve_signals(v_output.ns) - v_file = build_name + ".v" - v_output.write(v_file) - sources = platform.sources | {(v_file, "verilog", "work")} - self._build_batch(platform, sources, build_name) - tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc)) - if run: - _run_vivado(build_name, vivado_path, source) - - os.chdir("..") - - return v_output.ns - - def add_period_constraint(self, platform, clk, period): - platform.add_platform_command("""create_clock -name {clk} -period """ + \ - str(period) + """ [get_ports {clk}]""", clk=clk) diff --git a/migen/build/__init__.py b/migen/build/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/migen/build/altera/__init__.py b/migen/build/altera/__init__.py new file mode 100644 index 00000000..9fc45d4a --- /dev/null +++ b/migen/build/altera/__init__.py @@ -0,0 +1,2 @@ +from migen.build.altera.platform import AlteraPlatform +from migen.build.altera.programmer import USBBlaster diff --git a/migen/build/altera/common.py b/migen/build/altera/common.py new file mode 100644 index 00000000..56e20655 --- /dev/null +++ b/migen/build/altera/common.py @@ -0,0 +1,38 @@ +from migen.fhdl.std import Instance, Module +from migen.genlib.io import DifferentialInput, DifferentialOutput + + +class QuartusDifferentialInputImpl(Module): + def __init__(self, i_p, i_n, o): + self.specials += Instance("ALT_INBUF_DIFF", + name="ibuf_diff", + i_i=i_p, + i_ibar=i_n, + o_o=o) + + +class QuartusDifferentialInput: + @staticmethod + def lower(dr): + return QuartusDifferentialInputImpl(dr.i_p, dr.i_n, dr.o) + + +class QuartusDifferentialOutputImpl(Module): + def __init__(self, i, o_p, o_n): + self.specials += Instance("ALT_OUTBUF_DIFF", + name="obuf_diff", + i_i=i, + o_o=o_p, + o_obar=o_n) + + +class QuartusDifferentialOutput: + @staticmethod + def lower(dr): + return QuartusDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) + + +altera_special_overrides = { + DifferentialInput: QuartusDifferentialInput, + DifferentialOutput: QuartusDifferentialOutput +} diff --git a/migen/build/altera/platform.py b/migen/build/altera/platform.py new file mode 100644 index 00000000..43841fa7 --- /dev/null +++ b/migen/build/altera/platform.py @@ -0,0 +1,27 @@ +from migen.build.generic_platform import GenericPlatform +from migen.build.altera import common, quartus + + +class AlteraPlatform(GenericPlatform): + bitstream_ext = ".sof" + + def __init__(self, *args, toolchain="quartus", **kwargs): + GenericPlatform.__init__(self, *args, **kwargs) + if toolchain == "quartus": + self.toolchain = quartus.AlteraQuartusToolchain() + else: + raise ValueError("Unknown toolchain") + + def get_verilog(self, *args, special_overrides=dict(), **kwargs): + so = dict(common.altera_special_overrides) + so.update(special_overrides) + return GenericPlatform.get_verilog(self, *args, special_overrides=so, + **kwargs) + + def build(self, *args, **kwargs): + return self.toolchain.build(self, *args, **kwargs) + + def add_period_constraint(self, clk, period): + if hasattr(clk, "p"): + clk = clk.p + self.toolchain.add_period_constraint(self, clk, period) diff --git a/migen/build/altera/programmer.py b/migen/build/altera/programmer.py new file mode 100644 index 00000000..369f7db1 --- /dev/null +++ b/migen/build/altera/programmer.py @@ -0,0 +1,13 @@ +import subprocess + +from migen.build.generic_programmer import GenericProgrammer + + +class USBBlaster(GenericProgrammer): + needs_bitreverse = False + + def load_bitstream(self, bitstream_file, port=0): + usb_port = "[USB-{}]".format(port) + subprocess.call(["quartus_pgm", "-m", "jtag", "-c", + "USB-Blaster{}".format(usb_port), "-o", + "p;{}".format(bitstream_file)]) diff --git a/migen/build/altera/quartus.py b/migen/build/altera/quartus.py new file mode 100644 index 00000000..aab2048b --- /dev/null +++ b/migen/build/altera/quartus.py @@ -0,0 +1,149 @@ +# This file is Copyright (c) 2013 Florent Kermarrec +# License: BSD + +import os +import subprocess + +from migen.fhdl.structure import _Fragment + +from migen.build.generic_platform import Pins, IOStandard, Misc +from migen.build import tools + + +def _format_constraint(c, signame, fmt_r): + if isinstance(c, Pins): + return "set_location_assignment -comment \"{name}\" " \ + "-to {signame} Pin_{pin}".format( + signame=signame, + name=fmt_r, + pin=c.identifiers[0]) + elif isinstance(c, IOStandard): + return "set_instance_assignment -name io_standard " \ + "-comment \"{name}\" \"{std}\" -to {signame}".format( + signame=signame, + name=fmt_r, + std=c.name) + elif isinstance(c, Misc): + if not isinstance(c.misc, str) and len(c.misc) == 2: + return "set_instance_assignment -comment \"{name}\" " \ + "-name {misc[0]} \"{misc[1]}\" -to {signame}".format( + signame=signame, + name=fmt_r, + misc=c.misc) + else: + return "set_instance_assignment -comment \"{name}\" " \ + "-name {misc} " \ + "-to {signame}".format( + signame=signame, + name=fmt_r, + misc=c.misc) + + +def _format_qsf(signame, pin, others, resname): + fmt_r = "{}:{}".format(*resname[:2]) + if resname[2] is not None: + fmt_r += "." + resname[2] + + fmt_c = [_format_constraint(c, signame, fmt_r) for c in + ([Pins(pin)] + others)] + + return '\n'.join(fmt_c) + + +def _build_qsf(named_sc, named_pc): + lines = [] + for sig, pins, others, resname in named_sc: + if len(pins) > 1: + for i, p in enumerate(pins): + lines.append( + _format_qsf("{}[{}]".format(sig, i), p, others, resname)) + else: + lines.append(_format_qsf(sig, pins[0], others, resname)) + + if named_pc: + lines.append("") + lines.append("\n\n".join(named_pc)) + + lines.append("set_global_assignment -name top_level_entity top") + return "\n".join(lines) + + +def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name): + lines = [] + for filename, language, library in sources: + # Enforce use of SystemVerilog + # (Quartus does not support global parameters in Verilog) + if language == "verilog": + language = "systemverilog" + lines.append( + "set_global_assignment -name {lang}_FILE {path} " + "-library {lib}".format( + lang=language.upper(), + path=filename.replace("\\", "/"), + lib=library)) + + for path in vincpaths: + lines.append("set_global_assignment -name SEARCH_PATH {}".format( + path.replace("\\", "/"))) + + lines.append(_build_qsf(named_sc, named_pc)) + lines.append("set_global_assignment -name DEVICE {}".format(device)) + tools.write_to_file("{}.qsf".format(build_name), "\n".join(lines)) + + +def _run_quartus(build_name, quartus_path): + build_script_contents = """# Autogenerated by Migen + +quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name} +quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name} +quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name} +quartus_sta {build_name} -c {build_name} + +""".format(build_name=build_name) # noqa + build_script_file = "build_" + build_name + ".sh" + tools.write_to_file(build_script_file, + build_script_contents, + force_unix=True) + + if subprocess.call(["bash", build_script_file]): + raise OSError("Subprocess failed") + + +class AlteraQuartusToolchain: + def build(self, platform, fragment, build_dir="build", build_name="top", + quartus_path="/opt/Altera", run=True): + tools.mkdir_noerror(build_dir) + os.chdir(build_dir) + + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + platform.finalize(fragment) + + v_output = platform.get_verilog(fragment) + named_sc, named_pc = platform.resolve_signals(v_output.ns) + v_file = build_name + ".v" + v_output.write(v_file) + sources = platform.sources | {(v_file, "verilog", "work")} + _build_files(platform.device, + sources, + platform.verilog_include_paths, + named_sc, + named_pc, + build_name) + if run: + _run_quartus(build_name, quartus_path) + + os.chdir("..") + + return v_output.ns + + def add_period_constraint(self, platform, clk, period): + # TODO: handle differential clk + platform.add_platform_command( + "set_global_assignment -name duty_cycle 50 -section_id {clk}", + clk=clk) + platform.add_platform_command( + "set_global_assignment -name fmax_requirement \"{freq} MHz\" " + "-section_id {clk}".format(freq=(1. / period) * 1000, + clk="{clk}"), + clk=clk) diff --git a/migen/build/fpgalink_programmer.py b/migen/build/fpgalink_programmer.py new file mode 100644 index 00000000..fc7586dc --- /dev/null +++ b/migen/build/fpgalink_programmer.py @@ -0,0 +1,102 @@ +import os + +from migen.build.generic_programmer import GenericProgrammer +from migen.build.xilinx.programmer import _create_xsvf + +try: + import fl +except ImportError: + import fpgalink3 as fl + +fl.flInitialise(0) + + +class FPGALink(GenericProgrammer): + """Using the fpgalink library from makestuff + + You will need fpgalink library installed from + https://github.com/makestuff/libfpgalink + """ + + needs_bitreverse = False + + def __init__(self, initial_vidpid=None, pin_cfg="D0D2D3D4", + fpgalink_vidpid="1D50:602B:0002", flash_proxy_basename=None): + """ + Parameters + ---------- + initial_vidpid : string + The USB vendor and product id of the device before fpgalink + firmware is loaded onto the device. + + Format is vid:pid as 4 digit hex numbers. + + pin_cfg : string + FPGALink pin configuration string describing how the JTAG interface + is hooked up to the programmer. + + fpgalink_vidpid : string + The USB vendor, product and device id of the device after the + fpgalink firmware is loaded onto the device. + + Format is vid:pid:did as 4 digit hex numbers. + Defaults to 1D50:602B:0002 which is the makestuff FPGALink device. + """ + GenericProgrammer.__init__(self, flash_proxy_basename) + self.initial_vidpid = initial_vidpid + self.fpgalink_vidpid = fpgalink_vidpid + self.pin_cfg = pin_cfg + + def open_device(self): + ivp = self.initial_vidpid + vp = self.fpgalink_vidpid + + print("Attempting to open connection to FPGALink device", vp, "...") + try: + handle = fl.flOpen(self.fpgalink_vidpid) + except fl.FLException as ex: + if not ivp: + raise FLException( + "Could not open FPGALink device at {0} and" + " no initial VID:PID was supplied".format(vp)) + + print("Loading firmware into %s..." % ivp) + fl.flLoadStandardFirmware(ivp, vp) + + print("Awaiting renumeration...") + if not fl.flAwaitDevice(vp, 600): + raise fl.FLException( + "FPGALink device did not renumerate properly" + " as {0}".format(vp)) + + print("Attempting to open connection to FPGALink device", vp, + "again...") + handle = fl.flOpen(vp) + + # Only Nero capable hardware support doing programming. + assert fl.flIsNeroCapable(handle) + print("Cable connection opened.") + return handle + + def load_bitstream(self, bitstream_file): + n = 27 + + xsvf_file = os.path.splitext(bitstream_file)[0]+'.xsvf' + print("\nGenerating xsvf formatted bitstream") + print("="*n) + if os.path.exists(xsvf_file): + os.unlink(xsvf_file) + _create_xsvf(bitstream_file, xsvf_file) + print("\n"+"="*n+"\n") + + print("Programming %s to device." % xsvf_file) + print("="*n) + handle = self.open_device() + print("Programming device...") + fl.flProgram(handle, "J:"+self.pin_cfg, progFile=xsvf_file) + print("Programming successful!") + print("="*n+"\n") + fl.flClose(handle) + + def flash(self, address, data_file): + raise NotImplementedError("Not supported yet.") diff --git a/migen/build/generic_platform.py b/migen/build/generic_platform.py new file mode 100644 index 00000000..ff8a51e3 --- /dev/null +++ b/migen/build/generic_platform.py @@ -0,0 +1,363 @@ +import os +import sys + +from migen.fhdl.std import Signal +from migen.genlib.record import Record +from migen.genlib.io import CRG +from migen.fhdl import verilog, edif +from migen.util.misc import autotype + +from migen.build import tools + + +class ConstraintError(Exception): + pass + + +class Pins: + def __init__(self, *identifiers): + self.identifiers = [] + for i in identifiers: + self.identifiers += i.split() + + def __repr__(self): + return "{}('{}')".format(self.__class__.__name__, + " ".join(self.identifiers)) + + +class IOStandard: + def __init__(self, name): + self.name = name + + def __repr__(self): + return "{}('{}')".format(self.__class__.__name__, self.name) + + +class Drive: + def __init__(self, strength): + self.strength = strength + + def __repr__(self): + return "{}('{}')".format(self.__class__.__name__, self.strength) + + +class Misc: + def __init__(self, misc): + self.misc = misc + + def __repr__(self): + return "{}({})".format(self.__class__.__name__, repr(self.misc)) + + +class Subsignal: + def __init__(self, name, *constraints): + self.name = name + self.constraints = list(constraints) + + def __repr__(self): + return "{}('{}', {})".format( + self.__class__.__name__, + self.name, + ", ".join([repr(constr) for constr in self.constraints])) + + +class PlatformInfo: + def __init__(self, info): + self.info = info + + def __repr__(self): + return "{}({})".format(self.__class__.__name__, repr(self.info)) + + +def _lookup(description, name, number): + for resource in description: + if resource[0] == name and (number is None or resource[1] == number): + return resource + raise ConstraintError("Resource not found: {}:{}".format(name, number)) + + +def _resource_type(resource): + t = None + for element in resource[2:]: + if isinstance(element, Pins): + assert(t is None) + t = len(element.identifiers) + elif isinstance(element, Subsignal): + if t is None: + t = [] + + assert(isinstance(t, list)) + n_bits = None + for c in element.constraints: + if isinstance(c, Pins): + assert(n_bits is None) + n_bits = len(c.identifiers) + + t.append((element.name, n_bits)) + + return t + + +class ConnectorManager: + def __init__(self, connectors): + self.connector_table = dict() + for connector in connectors: + cit = iter(connector) + conn_name = next(cit) + if isinstance(connector[1], str): + pin_list = [] + for pins in cit: + pin_list += pins.split() + pin_list = [None if pin == "None" else pin for pin in pin_list] + elif isinstance(connector[1], dict): + pin_list = connector[1] + else: + raise ValueError("Unsupported pin list type {} for connector" + " {}".format(type(connector[1]), conn_name)) + if conn_name in self.connector_table: + raise ValueError( + "Connector specified more than once: {}".format(conn_name)) + + self.connector_table[conn_name] = pin_list + + def resolve_identifiers(self, identifiers): + r = [] + for identifier in identifiers: + if ":" in identifier: + conn, pn = identifier.split(":") + if pn.isdigit(): + pn = int(pn) + + r.append(self.connector_table[conn][pn]) + else: + r.append(identifier) + + return r + + +def _separate_pins(constraints): + pins = None + others = [] + for c in constraints: + if isinstance(c, Pins): + assert(pins is None) + pins = c.identifiers + else: + others.append(c) + + return pins, others + + +class ConstraintManager: + def __init__(self, io, connectors): + self.available = list(io) + self.matched = [] + self.platform_commands = [] + self.connector_manager = ConnectorManager(connectors) + + def add_extension(self, io): + self.available.extend(io) + + def request(self, name, number=None): + resource = _lookup(self.available, name, number) + rt = _resource_type(resource) + if isinstance(rt, int): + obj = Signal(rt, name_override=resource[0]) + else: + obj = Record(rt, name=resource[0]) + + for element in resource[2:]: + if isinstance(element, PlatformInfo): + obj.platform_info = element.info + break + + self.available.remove(resource) + self.matched.append((resource, obj)) + return obj + + def lookup_request(self, name, number=None): + for resource, obj in self.matched: + if resource[0] == name and (number is None or + resource[1] == number): + return obj + + raise ConstraintError("Resource not found: {}:{}".format(name, number)) + + def add_platform_command(self, command, **signals): + self.platform_commands.append((command, signals)) + + def get_io_signals(self): + r = set() + for resource, obj in self.matched: + if isinstance(obj, Signal): + r.add(obj) + else: + r.update(obj.flatten()) + + return r + + def get_sig_constraints(self): + r = [] + for resource, obj in self.matched: + name = resource[0] + number = resource[1] + has_subsignals = False + top_constraints = [] + for element in resource[2:]: + if isinstance(element, Subsignal): + has_subsignals = True + else: + top_constraints.append(element) + + if has_subsignals: + for element in resource[2:]: + if isinstance(element, Subsignal): + sig = getattr(obj, element.name) + pins, others = _separate_pins(top_constraints + + element.constraints) + pins = self.connector_manager.resolve_identifiers(pins) + r.append((sig, pins, others, + (name, number, element.name))) + else: + pins, others = _separate_pins(top_constraints) + pins = self.connector_manager.resolve_identifiers(pins) + r.append((obj, pins, others, (name, number, None))) + + return r + + def get_platform_commands(self): + return self.platform_commands + + +class GenericPlatform: + def __init__(self, device, io, connectors=[], name=None): + self.device = device + self.constraint_manager = ConstraintManager(io, connectors) + if name is None: + name = self.__module__.split(".")[-1] + self.name = name + self.sources = set() + self.verilog_include_paths = set() + self.finalized = False + + def request(self, *args, **kwargs): + return self.constraint_manager.request(*args, **kwargs) + + def lookup_request(self, *args, **kwargs): + return self.constraint_manager.lookup_request(*args, **kwargs) + + def add_period_constraint(self, clk, period): + raise NotImplementedError + + def add_platform_command(self, *args, **kwargs): + return self.constraint_manager.add_platform_command(*args, **kwargs) + + def add_extension(self, *args, **kwargs): + return self.constraint_manager.add_extension(*args, **kwargs) + + def finalize(self, fragment, *args, **kwargs): + if self.finalized: + raise ConstraintError("Already finalized") + # if none exists, create a default clock domain and drive it + if not fragment.clock_domains: + if not hasattr(self, "default_clk_name"): + raise NotImplementedError( + "No default clock and no clock domain defined") + crg = CRG(self.request(self.default_clk_name)) + fragment += crg.get_fragment() + + self.do_finalize(fragment, *args, **kwargs) + self.finalized = True + + def do_finalize(self, fragment, *args, **kwargs): + """overload this and e.g. add_platform_command()'s after the modules + had their say""" + if hasattr(self, "default_clk_period"): + try: + self.add_period_constraint( + self.lookup_request(self.default_clk_name), + self.default_clk_period) + except ConstraintError: + pass + + def add_source(self, filename, language=None, library=None): + if language is None: + language = tools.language_by_filename(filename) + + if language is None: + language = "verilog" # default to Verilog + + if library is None: + library = "work" # default to work + + filename = os.path.abspath(filename) + if sys.platform == "win32" or sys.platform == "cygwin": + filename = filename.replace("\\", "/") + self.sources.add((filename, language, library)) + + def add_sources(self, path, *filenames, language=None, library=None): + for f in filenames: + self.add_source(os.path.join(path, f), language, library) + + def add_source_dir(self, path, recursive=True, library=None): + dir_files = [] + if recursive: + for root, dirs, files in os.walk(path): + for filename in files: + dir_files.append(os.path.join(root, filename)) + else: + for item in os.listdir(path): + if os.path.isfile(os.path.join(path, item)): + dir_files.append(os.path.join(path, item)) + for filename in dir_files: + language = tools.language_by_filename(filename) + if language is not None: + self.add_source(filename, language, library) + + def add_verilog_include_path(self, path): + path = os.path.abspath(path) + if sys.platform == "win32" or sys.platform == "cygwin": + path = path.replace("\\", "/") + self.verilog_include_paths.add(path) + + def resolve_signals(self, vns): + # resolve signal names in constraints + sc = self.constraint_manager.get_sig_constraints() + named_sc = [(vns.get_name(sig), pins, others, resource) + for sig, pins, others, resource in sc] + # resolve signal names in platform commands + pc = self.constraint_manager.get_platform_commands() + named_pc = [] + for template, args in pc: + name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items()) + named_pc.append(template.format(**name_dict)) + + return named_sc, named_pc + + def get_verilog(self, fragment, **kwargs): + return verilog.convert( + fragment, + self.constraint_manager.get_io_signals(), + create_clock_domains=False, **kwargs) + + def get_edif(self, fragment, cell_library, vendor, device, **kwargs): + return edif.convert( + fragment, + self.constraint_manager.get_io_signals(), + cell_library, vendor, device, **kwargs) + + def build(self, fragment): + raise NotImplementedError("GenericPlatform.build must be overloaded") + + def build_cmdline(self, *args, **kwargs): + arg = sys.argv[1:] + if len(arg) % 2: + print("Missing value for option: {}".format(sys.argv[-1])) + sys.exit(1) + + argdict = dict((k, autotype(v)) for k, v in zip(*[iter(arg)] * 2)) + kwargs.update(argdict) + self.build(*args, **kwargs) + + def create_programmer(self): + raise NotImplementedError diff --git a/migen/build/generic_programmer.py b/migen/build/generic_programmer.py new file mode 100644 index 00000000..82a1ebe0 --- /dev/null +++ b/migen/build/generic_programmer.py @@ -0,0 +1,31 @@ +import os + + +class GenericProgrammer: + def __init__(self, flash_proxy_basename=None): + self.flash_proxy_basename = flash_proxy_basename + self.flash_proxy_dirs = [ + "~/.migen", "/usr/local/share/migen", "/usr/share/migen", + "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs"] + + def set_flash_proxy_dir(self, flash_proxy_dir): + if flash_proxy_dir is not None: + self.flash_proxy_dirs = [flash_proxy_dir] + + def find_flash_proxy(self): + for d in self.flash_proxy_dirs: + fulldir = os.path.abspath(os.path.expanduser(d)) + fullname = os.path.join(fulldir, self.flash_proxy_basename) + if os.path.exists(fullname): + return fullname + raise OSError("Failed to find flash proxy bitstream") + + # must be overloaded by specific programmer + def load_bitstream(self, bitstream_file): + raise NotImplementedError + + # must be overloaded by specific programmer + def flash(self, address, data_file): + raise NotImplementedError + + diff --git a/migen/build/lattice/__init__.py b/migen/build/lattice/__init__.py new file mode 100644 index 00000000..78b2035d --- /dev/null +++ b/migen/build/lattice/__init__.py @@ -0,0 +1,2 @@ +from migen.build.lattice.platform import LatticePlatform +from migen.build.lattice.programmer import LatticeProgrammer diff --git a/migen/build/lattice/common.py b/migen/build/lattice/common.py new file mode 100644 index 00000000..090d3fc0 --- /dev/null +++ b/migen/build/lattice/common.py @@ -0,0 +1,41 @@ +from migen.fhdl.std import * +from migen.genlib.io import * + +from migen.genlib.resetsync import AsyncResetSynchronizer + + +class LatticeAsyncResetSynchronizerImpl(Module): + def __init__(self, cd, async_reset): + rst1 = Signal() + self.specials += [ + Instance("FD1S3BX", i_D=0, i_PD=async_reset, + i_CK=cd.clk, o_Q=rst1), + Instance("FD1S3BX", i_D=rst1, i_PD=async_reset, + i_CK=cd.clk, o_Q=cd.rst) + ] + + +class LatticeAsyncResetSynchronizer: + @staticmethod + def lower(dr): + return LatticeAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) + + +class LatticeDDROutputImpl(Module): + def __init__(self, i1, i2, o, clk): + self.specials += Instance("ODDRXD1", + synthesis_directive="ODDRAPPS=\"SCLK_ALIGNED\"", + i_SCLK=clk, + i_DA=i1, i_DB=i2, o_Q=o, + ) + + +class LatticeDDROutput: + @staticmethod + def lower(dr): + return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) + +lattice_special_overrides = { + AsyncResetSynchronizer: LatticeAsyncResetSynchronizer, + DDROutput: LatticeDDROutput +} diff --git a/migen/build/lattice/diamond.py b/migen/build/lattice/diamond.py new file mode 100644 index 00000000..098c67de --- /dev/null +++ b/migen/build/lattice/diamond.py @@ -0,0 +1,104 @@ +# This file is Copyright (c) 2015 Florent Kermarrec +# License: BSD + +import os +import subprocess +import shutil + +from migen.fhdl.structure import _Fragment + +from migen.build.generic_platform import * +from migen.build import tools +from migen.build.lattice import common + + +def _format_constraint(c): + if isinstance(c, Pins): + return ("LOCATE COMP ", " SITE " + "\"" + c.identifiers[0] + "\"") + elif isinstance(c, IOStandard): + return ("IOBUF PORT ", " IO_TYPE=" + c.name) + elif isinstance(c, Misc): + return c.misc + + +def _format_lpf(signame, pin, others, resname): + fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)] + r = "" + for pre, suf in fmt_c: + r += pre + "\"" + signame + "\"" + suf + ";\n" + return r + + +def _build_lpf(named_sc, named_pc): + r = "BLOCK RESETPATHS;\n" + r += "BLOCK ASYNCPATHS;\n" + for sig, pins, others, resname in named_sc: + if len(pins) > 1: + for i, p in enumerate(pins): + r += _format_lpf(sig + "[" + str(i) + "]", p, others, resname) + else: + r += _format_lpf(sig, pins[0], others, resname) + if named_pc: + r += "\n" + "\n\n".join(named_pc) + return r + + +def _build_files(device, sources, vincpaths, build_name): + tcl = [] + tcl.append("prj_project new -name \"{}\" -impl \"implementation\" -dev {} -synthesis \"synplify\"".format(build_name, device)) + for path in vincpaths: + tcl.append("prj_impl option {include path} {\"" + path + "\"}") + for filename, language, library in sources: + tcl.append("prj_src add \"" + filename + "\" -work " + library) + tcl.append("prj_run Synthesis -impl implementation -forceOne") + tcl.append("prj_run Translate -impl implementation") + tcl.append("prj_run Map -impl implementation") + tcl.append("prj_run PAR -impl implementation") + tcl.append("prj_run Export -impl implementation -task Bitgen") + tools.write_to_file(build_name + ".tcl", "\n".join(tcl)) + + +def _run_diamond(build_name, source, ver=None): + if sys.platform == "win32" or sys.platform == "cygwin": + build_script_contents = "REM Autogenerated by Migen\n" + build_script_contents = "pnmainc " + build_name + ".tcl\n" + build_script_file = "build_" + build_name + ".bat" + tools.write_to_file(build_script_file, build_script_contents) + r = subprocess.call([build_script_file]) + shutil.copy(os.path.join("implementation", build_name + "_implementation.bit"), build_name + ".bit") + else: + raise NotImplementedError + + if r != 0: + raise OSError("Subprocess failed") + + +class LatticeDiamondToolchain: + def build(self, platform, fragment, build_dir="build", build_name="top", + diamond_path="/opt/Diamond", run=True): + tools.mkdir_noerror(build_dir) + os.chdir(build_dir) + + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + platform.finalize(fragment) + + v_output = platform.get_verilog(fragment) + named_sc, named_pc = platform.resolve_signals(v_output.ns) + v_file = build_name + ".v" + v_output.write(v_file) + sources = platform.sources | {(v_file, "verilog", "work")} + _build_files(platform.device, sources, platform.verilog_include_paths, build_name) + + tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc)) + + if run: + _run_diamond(build_name, diamond_path) + + os.chdir("..") + + return v_output.ns + + def add_period_constraint(self, platform, clk, period): + # TODO: handle differential clk + platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk) diff --git a/migen/build/lattice/platform.py b/migen/build/lattice/platform.py new file mode 100644 index 00000000..73742231 --- /dev/null +++ b/migen/build/lattice/platform.py @@ -0,0 +1,26 @@ +from migen.build.generic_platform import GenericPlatform +from migen.build.lattice import common, diamond + + +class LatticePlatform(GenericPlatform): + bitstream_ext = ".bit" + + def __init__(self, *args, toolchain="diamond", **kwargs): + GenericPlatform.__init__(self, *args, **kwargs) + if toolchain == "diamond": + self.toolchain = diamond.LatticeDiamondToolchain() + else: + raise ValueError("Unknown toolchain") + + def get_verilog(self, *args, special_overrides=dict(), **kwargs): + so = dict(common.lattice_special_overrides) + so.update(special_overrides) + return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) + + def build(self, *args, **kwargs): + return self.toolchain.build(self, *args, **kwargs) + + def add_period_constraint(self, clk, period): + if hasattr(clk, "p"): + clk = clk.p + self.toolchain.add_period_constraint(self, clk, period) diff --git a/migen/build/lattice/programmer.py b/migen/build/lattice/programmer.py new file mode 100644 index 00000000..cc3c50bd --- /dev/null +++ b/migen/build/lattice/programmer.py @@ -0,0 +1,54 @@ +import os +import subprocess + +from migen.build.generic_programmer import GenericProgrammer +from migen.build import tools + + +# XXX Lattice programmer need an .xcf file, will need clean up and support for more parameters +_xcf_template = """ + + + + + + JTAG + + + 1 + Lattice + LatticeECP3 + LFE3-35EA + {bitstream_file} + Fast Program + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + USB2 + FTUSB-0 + Dual RS232-HS A Location 0000 Serial A + + TRST ABSENT; + ISPEN ABSENT; + + + +""" + + +class LatticeProgrammer(GenericProgrammer): + needs_bitreverse = False + + def load_bitstream(self, bitstream_file): + xcf_file = bitstream_file.replace(".bit", ".xcf") + xcf_content = _xcf_template.format(bitstream_file=bitstream_file) + tools.write_to_file(xcf_file, xcf_content) + subprocess.call(["pgrcmd", "-infile", xcf_file]) diff --git a/migen/build/openocd.py b/migen/build/openocd.py new file mode 100644 index 00000000..aec29980 --- /dev/null +++ b/migen/build/openocd.py @@ -0,0 +1,30 @@ +import subprocess + +from migen.build.generic_programmer import GenericProgrammer + + +class OpenOCD(GenericProgrammer): + needs_bitreverse = False + + def __init__(self, config, flash_proxy_basename=None): + GenericProgrammer.__init__(self, flash_proxy_basename) + self.config = config + + def load_bitstream(self, bitstream): + script = "; ".join([ + "init", + "pld load 0 {}".format(bitstream), + "exit", + ]) + subprocess.call(["openocd", "-f", self.config, "-c", script]) + + def flash(self, address, data): + flash_proxy = self.find_flash_proxy() + script = "; ".join([ + "init", + "jtagspi_init 0 {}".format(flash_proxy), + "jtagspi_program {} 0x{:x}".format(data, address), + "fpga_program", + "exit" + ]) + subprocess.call(["openocd", "-f", self.config, "-c", script]) diff --git a/migen/build/platforms/__init__.py b/migen/build/platforms/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/migen/build/platforms/apf27.py b/migen/build/platforms/apf27.py new file mode 100644 index 00000000..ea182e21 --- /dev/null +++ b/migen/build/platforms/apf27.py @@ -0,0 +1,150 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_ios = [ + ("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")), + ("fpga_reset", 0, Pins("T9"), IOStandard("LVCMOS18"), Drive("8")), + ("fpga_initb", 0, Pins("T12"), IOStandard("LVCMOS18"), Drive("8")), + ("weim", 0, + Subsignal("cs4_dtack", Pins("R3"), IOStandard("LVCMOS18"), Drive("8")), + Subsignal("cs5n", Pins("P10"), IOStandard("LVCMOS18")), + Subsignal("eb0n", Pins("P9"), IOStandard("LVCMOS18")), + Subsignal("oen", Pins("R9"), IOStandard("LVCMOS18")), + Subsignal("data", + Pins("T5 T6 P7 N8 P12 T13 R13 T14 P5 N6 T3 T11 T4 R5 M10 T10"), + IOStandard("LVCMOS18"), Drive("8")), + Subsignal("addr", + Pins("N5 L7 M7 M8 L8 L9 L10 M11 P11 N11 N12 P13"), + IOStandard("LVCMOS18")) + ) +] + +_connectors = [ + ("J2", + "None", # no 0 pin + "None", # 1 +3v3 + "None", # 2 +3v3 + "None", # 3 GND + "None", # 4 GND + "None", # 5 DP USB_OTG_PHY +3V3 + "None", # 6 DM USB_OTG_PHY +3V3 + "None", # 7 VBUS USB_OTG_ PHY +3V3 + "None", # 8 PSW_N USB_OTG_PHY +3V3 + "None", # 9 ID USB_OTG_PHY +3V3 + "None", # 10 FAULT USB_OTG_PHY +3V3 + "None", # 11 RXP Ethernet_PHY +3V3 + "None", # 12 RXN Ethernet_PHY +3V3 + "None", # 13 ETH_LINK Ethernet_PHY +2V8 + "None", # 14 PC_VS2 PC +2V8 PF13 + "None", # 15 PC_VS1 PC +2V8 PF14 + "None", # 16 PC_PWRON PC +2V8 PF16 + "None", # 17 PC_READY PC +2V8 PF17 + "None", # 18 PWM0 PWM0 +2V8 PE5 + "None", # 19 TOUT GPT +2V8 PC14 + "None", # 20 GND POWER + "None", # 21 VCC01 (IN) BANK1 SUPPLY VCCO1 + "C16", # 22 IO_L24P_1 FPGA_BANK1 VCC01 + "C15", # 23 IO_L24N_1 FPGA_BANK1 VCC01 + "D16", # 24 IO_L22_P1 FPGA_BANK1 VCC01 + "None", # 25 GND POWER + "B14", # 26 IO_L02N_0 FPGA_BANK0 VCCO0 + "B15", # 27 IO_L02P_0 FPGA_BANK0 + "A13", # 28 IO_L04N_0 FPGA_BANK0 + "A14", # 29 IO_L04P_0 FPGA_BANK0 VCCO0 + "D11", # 30 IO_L03N_0 FPGA_BANK0 VCCO0 + "C12", # 31 IO_L03P_0 FPGA_BANK0 VCCO0 + "A10", # 32 IO_L08N_0 FPGA_BANK0 VCCO0 + "B10", # 33 IO_L08P_0 FPGA_BANK0 VCCO0 + "A9", # 34 IO_L10N_0 / GLCK7 FPGA_BANK0 VCCO0 + "C9", # 35 IO_L10P_0 / GCLK6 FPGA_BANK0 VCCO0 + "B8", # 36 IO_L12N_0 / GCLK11 FPGA_BANK0 VCCO0 + "A8", # 37 IO_L12P_0 / GCLK10 FPGA_BANK0 VCCO0 + "B6", # 38 IO_L15N_0 FPGA_BANK0 VCCO0 + "A6", # 39 IO_L15P_0 FPGA_BANK0 VCCO0 + "B4", # 40 IO_L18N_0 FPGA_BANK0 VCCO0 + "A4", # 41 IO_L18P_0 FPGA_BANK0 VCCO0 + "None", # 42 GND POWER + "N3", # 43 IO_L24P_3 FPGA_BANK3 VCCO3 + "R1", # 44 IO_L23P_3 FPGA_BANK3 VCCO3 + "P1", # 45 IO_L22N_3 FPGA_BANK3 VCCO3 + "N1", # 46 IO_L20N_3 FPGA_BANK3 VCCO3 + "M1", # 47 IO_L20P_3 FPGA_BANK3 VCCO3 + "H3", # 48 IO_L12P_3 FPGA_BANK3 VCCO3 + "K1", # 49 IO_L15N_3 FPGA_BANK3 VCCO3 + "J1", # 50 IO_L14N_3 FPGA_BANK3 VCCO3 + "H1", # 51 IO_L11N_3 FPGA_BANK3 VCCO3 + "G1", # 52 IO_L08N_3 FPGA_BANK3 VCCO3 + "F1", # 53 IO_L08P_3 FPGA_BANK3 VCCO3 + "E1", # 54 IO_L03N_3 FPGA_BANK3 VCCO3 + "D1", # 55 IO_LO3P_3 FPGA_BANK3 VCCO3 + "C1", # 56 IO_L01N_3 FPGA_BANK3 VCCO3 + "None", # 57 GND POWER + "None", # 58 TRSTN JTAG +2V8 + "None", # 59 TDI JTAG +2V8 + "None", # 60 TCK JTAG +2V8 + "None", # 61 TDO JTAG +2V8 + "None", # 62 TMS JTAG +2V8 + "None", # 63 GND POWER + "C2", # 64 IO_L01P_3 FPGA_BANK3 VCCO3 + "D3", # 65 IO_L02N_3 FPGA_BANK3 VCCO3 + "D4", # 66 IO_L02P_3 FPGA_BANK3 VCCO3 + "F4", # 67 IP_LO4N_3 FPGA_BANK3 VCCO3 + "G2", # 68 IO_L11P_3 FPGA_BANK3 VCCO3 + "J2", # 69 IO_L14P_3 FPGA_BANK3 VCCO3 + "K3", # 70 IO_L15P_3 FPGA_BANK3 VCCO3 + "J3", # 71 IO_L12N_3 FPGA_BANK3 VCCO3 + "N2", # 72 IO_L22P_3 FPGA_BANK3 VCCO3 + "P2", # 73 IO_L23N_3 FPGA_BANK3 VCCO3 + "M4", # 74 IO_L24N_3 FPGA_BANK3 VCCO3 + "L6", # 75 IP_L25N_3 FPGA_BANK3 VCCO3 + "None", # 76 VCCO3 (IN) BANK3 SUPPLY VCCO3 (3.3Vmax) + "None", # 77 VCCO3 (IN) BANK3 SUPPLY VCCO3 (3.3Vmax) + "A3", # 78 IO_L19P_0 FPGA_BANK0 VCCO0 + "B3", # 79 IO_L19N_0 FPGA_BANK0 VCCO0 + "A5", # 80 IO_L17P_0 FPGA_BANK0 VCCO0 + "C5", # 81 IO_L17N_0 FPGA_BANK0 VCCO0 + "D7", # 82 IO_L16P_0 FPGA_BANK0 VCCO0 + "C6", # 83 IO_L16N_0 FPGA_BANK0 VCCO0 + "C8", # 84 IO_L11P_0 / GCLK8 FPGA_BANK0 VCCO0 + "D8", # 85 IO_L11N_0 / GCLK9 FPGA_BANK0 VCCO0 + "C10", # 86 IO_L09P_0 / GCLK4 FPGA_BANK0 VCCO0 + "D9", # 87 IO_L09N_0 / GCLK5 FPGA_BANK0 VCCO0 + "C11", # 88 IO_L07P_0 FPGA_BANK0 VCCO0 + "A11", # 89 IO_L07N_0 FPGA_BANK0 VCCO0 + "D13", # 90 IO_L01P_0 FPGA_BANK0 VCCO0 + "C13", # 91 IO_L01N_0 FPGA_BANK0 VCCO0 + "None", # 92 VCCO0 (IN) BANK0 SUPPLY VCCO0 (3.3Vmax) + "None", # 93 VCCO0 (IN) BANK0 SUPPLY VCCO0 (3.3Vmax) + "None", # 94 GND POWER VCCO0 A13 + "D15", # 95 IO_L22N_1 FPGA_BANK1 VCC01 + "E13", # 96 IO_L23P_1 FPGA_BANK1 VCC01 + "D14", # 97 IO_L23N_1 FPGA_BANK1 VCC01 + "E14", # 98 IO_L20P_1 FPGA_BANK1 VCC01 + "F13", # 99 IO_L20N_1 FPGA_BANK1 VCC01 + "None", # 100 GND POWER (3.3Vmax) + "None", # 101 USR_RESETN (open CONFIG Pos PC15 +2V8 drain with pullup) + "None", # 102 TIN GPT +2V8 + "None", # 103 EXTAL_26M CONFIG +2V5 + "None", # 104 RX3 RS232_3 RS232 + "None", # 105 TX3 RS232_3 RS232 + "None", # 106 RX1 RS232_1 RS232 + "None", # 107 TX1 RS232_1 RS232 + "None", # 108 BOOT CONFIG +2V8 + "None", # 109 TXN Ethernet_PHY +3V3 + "None", # 110 TXP Ethernet_PHY +3V3 + "None", # 111 ETH_ACTIVITY Ethernet_PHY +2V8 + "None", # 112 USBH2_NXT USB_HOST2 +2V5 PA3 + "None", # 113 USBH2_DIR USB_HOST2 +2V5 PA1 + "None", # 114 USBH2_DATA7 USB_HOST2 +2V5 PA2 + "None", # 115 USBH2_STP USB_HOST2 +2V5 PA4 + "None") # 116 USBH2_CLK USB_HOST2 +2V5 PA0 +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk0" + default_clk_period = 10 + + def __init__(self): + XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors) diff --git a/migen/build/platforms/apf51.py b/migen/build/platforms/apf51.py new file mode 100644 index 00000000..f776cdac --- /dev/null +++ b/migen/build/platforms/apf51.py @@ -0,0 +1,177 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_ios = [ + ("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")), + ("clko", 0, Pins("N7"), IOStandard("LVCMOS33")), + ("fpga_initb", 0, Pins("P3"), IOStandard("LVCMOS33")), + ("fpga_program", 0, Pins("R2"), IOStandard("LVCMOS33")), + ("eim", 0, + Subsignal("bclk", Pins("N12")), + Subsignal("eb1", Pins("P13")), + Subsignal("cs1", Pins("R11")), + Subsignal("cs2", Pins("N9")), + Subsignal("lba", Pins("R9")), + Subsignal("eb0", Pins("P7")), + Subsignal("oe", Pins("R7")), + Subsignal("rw", Pins("R6")), + Subsignal("dtack", Pins("N4")), + Subsignal("wait", Pins("R4")), + Subsignal("da", Pins("N6 L5 L6 R5 P5 N11 M11 P11 L8 K8 M8 M10 L9 R10 N5 M5")), + IOStandard("LVCMOS33") + ) +] + +_connectors = [ + ("J2", + "None", # No 0 pin + "None", # 1 FPGA Bank1 power + "None", # 2 FPGA Bank1 power + "None", # 3 GND + "B14", # 4 IO_L1P_A25_1 + "B15", # 5 IO_L1N_A24_VREF_1 + "C14", # 6 IO_L33P_A15_M1A10_1 + "C15", # 7 IO_L33N_A14_M1A4_1 + "D13", # 8 IO_L35P_A11_M1A7_1 + "D15", # 9 IO_L35N_A10_M1A2_1 + "E14", # 10 IO_L37P_A7_M1A0_1 + "E15", # 11 IO_L37N_A6_M1A1_1 + "None", # 12 GND + "F13", # 13 IO_L39P_M1A3_1 + "F15", # 14 IO_L39N_M1ODT_1 + "G14", # 15 IO_L41P_GCLK9_IRDY1_M1RASN_1 + "G15", # 16 IO_L41N_GCLK8_M1CASN_1 + "H13", # 17 IO_L42P_GCLK7_M1UDM_1 + "H15", # 18 IO_L42N_GCLK6_TRDY1_M1LDM + "J14", # 19 IO_L43P_GCLK5_M1DQ4_1 + "J15", # 20 IO_L43N_GCLK4_M1DQ5_1 + "K13", # 21 IO_L44P_A3_M1DQ6_1 + "K15", # 22 IO_L44N_A2_M1DQ7_1 + "L14", # 23 IO_L45P_A1_M1LDQS_1 + "L15", # 24 IO_L45N_A0_M1LDQSN_1 + "None", # 25 GND + "E2", # 26 IO_L52P_M3A8_3 + "E1", # 27 IO_L52N_M3A9_3 + "D3", # 28 IO_L54P_M3RESET_3 + "D1", # 29 IO_L54N_M3A11_3 + "F3", # 30 IO_L46P_M3CLK_3 + "F1", # 31 IO_L46N_M3CLKN_3 + "G2", # 32 IO_L44P_GCLK21_M3A5_3 + "G1", # 33 IO_L44N_GCLK20_M3A6_3 + "H3", # 34 IO_L42P_GCLK25_TRDY2_M3UDM_3 + "H1", # 35 IO_L42N_GCLK24_M3LDM_3 + "K3", # 36 IO_L40P_M3DQ6_3 + "K1", # 37 IO_L40N_M3DQ7_3 + "None", # 38 GND + "None", # 39 GPIO4_16 + "None", # 40 GPIO4_17 + "None", # 41 BOOT_MODE0 + "None", # 42 AUD5_RXFS + "None", # 43 AUD5_RXC + "None", # 44 GND + "None", # 45 AUD5_RXD + "None", # 46 AUD5_TXC + "None", # 47 AUD5_TXFS + "None", # 48 GND + "None", # 49 SPI2_SCLK_GPT_CMPOUT3 + "None", # 50 SPI2_MISO + "None", # 51 SPI2_MOSI + "None", # 52 SPI2_SS1 + "None", # 53 SPI2_SS2 + "None", # 54 SPI2_SS3 + "None", # 55 SPI2_RDY + "None", # 56 OWIRE + "None", # 57 GND + "None", # 58 SPI1_SCLK + "None", # 59 SPI1_MISO + "None", # 60 SPI1_MOSI + "None", # 61 SPI1_SS0 + "None", # 62 SPI1_SS1 + "None", # 63 SPI1_RDY + "None", # 64 RESET# + "None", # 65 VIO_H2 + "None", # 66 PMIC_GPIO6 + "None", # 67 TOUCH_X+ + "None", # 68 TOUCH_X- + "None", # 69 TOUCH_Y+ + "None", # 70 TOUCH_Y- + "None", # 71 AUXADCIN4 + "None", # 72 AUXADCIN3 + "None", # 73 AUXADCIN2 + "None", # 74 AUXADCIN1 + "None", # 75 PMIC_GPIO7 + "None", # 76 +1v8 + "None", # 77 RESERVED + "None", # 78 UART3_TXD + "None", # 79 UART_3_RXD + "None", # 80 UART2_TXD + "None", # 81 UART2_RXD + "None", # 82 UART2_RTS_KEY_COL7 + "None", # 83 UART2_CTS_KEY_COL6 + "None", # 84 UART1_TXD + "None", # 85 UART1_RXD + "None", # 86 UART1_RTS + "None", # 87 UART1_CTS + "None", # 88 GND + "None", # 89 AUD3_TXD + "None", # 90 AUD3_RXD + "None", # 91 AUD3_FS + "None", # 92 AUD3_CK + "None", # 93 GND + "None", # 94 AUD6_TXFS_KEY_ROW7 + "None", # 95 AUD6_TXC_KEY_ROW6 + "None", # 96 AUD6_RXD_KEY_ROW5 + "None", # 97 AUD6_TXD_KEY_ROW4 + "None", # 98 I2C2_SDA_UART3_CTS + "None", # 99 I2C2_SCL_UART3_RTS + "None", # 100 BOOT_MODE1 + "None", # 101 PWM2 + "None", # 102 PWM1 + "None", # 103 GND + "L1", # 104 IO_L39N_M3LDQSN_3 + "L2", # 105 IO_L39P_M3LDQS_3 + "J1", # 106 IO_L41N_GCLK26_M3DQ5_3 + "J2", # 107 IO_L41P_GCLK27_M3DQ4_3 + "J3", # 108 IO_L43N_GCLK22_IRDY2_M3CASN_3 + "K4", # 109 IO_L43P_GCLK23_M3RASN_3 + "J4", # 110 IO_L45N_M3ODT_3 + "K5", # 111 IO_L45P_M3A3_3 + "C1", # 112 IO_L83N_VREF_3 + "C2", # 113 IO_L83P_3 + "E3", # 114 IO_L53N_M3A12_3 + "D4", # 115 IO_L53P_M3CKE_3 + "None", # 116 GND + "P15", # 117 IO_L74N_DOUT_BUSY_1 + "P14", # 118 IO_L74P_AWAKE_1 + "N15", # 119 IO_L47N_LDC_M1DQ1_1 + "N14", # 120 IO_L47P_FWE_B_M1DQ0_1 + "M15", # 121 IO_L46N_FOE_B_M1DQ3_1 + "M13", # 122 IO_L46P_FCS_B_M1DQS2_1 + "L12", # 123 IO_L40N_GCLK10_M1A6_1 + "K12", # 124 IO_L40P_GCLK11_M1A5_1 + "K11", # 125 IO_L38N_A4_M1CLKN_1 + "K10", # 126 IO_L38P_A5_M1CLK_1 + "J13", # 127 IO_L36N_A8_M1BA1_1 + "J11", # 128 IO_L36P_A9_M1BA0_1 + "None", # 129 GND + "G13", # 130 IO_L34N_A12_M1BA2_1_NOTLX4 + "H12", # 131 IO_L34P_A13_M1WE_1_NOTLX4 + "H11", # 132 IO_L32N_A16_M1A9_1_NOTLX4 + "H10", # 133 IO_L32P_A17_M1A8_1_NOTLX4 + "F12", # 134 IO_L31N_A18_M1A12_1_NOTLX4 + "F11", # 135 IO_L31P_A19_M1CKE_1_NOTLX4 + "G12", # 136 IO_L30N_A20_M1A11_1_NOTLX4 + "G11", # 137 IO_L30P_A21_M1RESET_1_NOTLX4 + "None", # 138 GND + "None", # 139 FPGA_BANK3_POWER + "None") # 140 FPGA_BANK3_POWER +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk3" + default_clk_period = 10.526 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors) diff --git a/migen/build/platforms/de0nano.py b/migen/build/platforms/de0nano.py new file mode 100644 index 00000000..4ef34daf --- /dev/null +++ b/migen/build/platforms/de0nano.py @@ -0,0 +1,103 @@ +# This file is Copyright (c) 2013 Florent Kermarrec +# License: BSD + +from migen.build.generic_platform import * +from migen.build.altera import AlteraPlatform +from migen.build.altera.programmer import USBBlaster + + +_io = [ + ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), + + ("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")), + ("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")), + ("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")), + ("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")), + ("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")), + ("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")), + ("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")), + ("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")), + + ("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")), + ("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")), + + ("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")), + ("sw", 1, Pins("T9"), IOStandard("3.3-V LVTTL")), + ("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")), + ("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")), + + ("serial", 0, + Subsignal("tx", Pins("D3"), IOStandard("3.3-V LVTTL")), + Subsignal("rx", Pins("C3"), IOStandard("3.3-V LVTTL")) + ), + + ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")), + Subsignal("ba", Pins("M7 M6")), + Subsignal("cs_n", Pins("P6")), + Subsignal("cke", Pins("L7")), + Subsignal("ras_n", Pins("L2")), + Subsignal("cas_n", Pins("L1")), + Subsignal("we_n", Pins("C2")), + Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")), + Subsignal("dm", Pins("R6 T5")), + IOStandard("3.3-V LVTTL") + ), + + ("epcs", 0, + Subsignal("data0", Pins("H2")), + Subsignal("dclk", Pins("H1")), + Subsignal("ncs0", Pins("D2")), + Subsignal("asd0", Pins("C1")), + IOStandard("3.3-V LVTTL") + ), + + ("i2c", 0, + Subsignal("sclk", Pins("F2")), + Subsignal("sdat", Pins("F1")), + IOStandard("3.3-V LVTTL") + ), + + ("g_sensor", 0, + Subsignal("cs_n", Pins("G5")), + Subsignal("int", Pins("M2")), + IOStandard("3.3-V LVTTL") + ), + + ("adc", 0, + Subsignal("cs_n", Pins("A10")), + Subsignal("saddr", Pins("B10")), + Subsignal("sclk", Pins("B14")), + Subsignal("sdat", Pins("A9")), + IOStandard("3.3-V LVTTL") + ), + + ("gpio_0", 0, + Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6", + "C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11", + "D12 B12"), + IOStandard("3.3-V LVTTL") + ), + ("gpio_1", 0, + Pins("F13 T15 T14 T13 R13 T12 R12 T11 T10 R11 P11 R10 N12 P9 N9 N11", + "L16 K16 R16 L15 P15 P16 R14 N16 N15 P14 L14 N14 M10 L13 J16 K15", + "J13 J14"), + IOStandard("3.3-V LVTTL") + ), + ("gpio_2", 0, + Pins("A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15"), + IOStandard("3.3-V LVTTL") + ), +] + + +class Platform(AlteraPlatform): + default_clk_name = "clk50" + default_clk_period = 20 + + def __init__(self): + AlteraPlatform.__init__(self, "EP4CE22F17C6", _io) + + def create_programmer(self): + return USBBlaster() diff --git a/migen/build/platforms/kc705.py b/migen/build/platforms/kc705.py new file mode 100644 index 00000000..eb51ab33 --- /dev/null +++ b/migen/build/platforms/kc705.py @@ -0,0 +1,458 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT +from migen.build.xilinx.ise import XilinxISEToolchain + + +_io = [ + ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), + ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), + ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), + ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")), + ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")), + ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")), + ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), + ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), + + ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), + + ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")), + ("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")), + ("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")), + ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")), + ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")), + + ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")), + ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")), + ("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")), + ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")), + + ("user_sma_clock", 0, + Subsignal("p", Pins("L25"), IOStandard("LVDS_25")), + Subsignal("n", Pins("K25"), IOStandard("LVDS_25")) + ), + ("user_sma_clock_p", 0, Pins("L25"), IOStandard("LVCMOS25")), + ("user_sma_clock_n", 0, Pins("K25"), IOStandard("LVCMOS25")), + + ("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS33")), + ("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS33")), + + ("clk200", 0, + Subsignal("p", Pins("AD12"), IOStandard("LVDS")), + Subsignal("n", Pins("AD11"), IOStandard("LVDS")) + ), + + ("clk156", 0, + Subsignal("p", Pins("K28"), IOStandard("LVDS_25")), + Subsignal("n", Pins("K29"), IOStandard("LVDS_25")) + ), + + ("i2c", 0, + Subsignal("scl", Pins("K21")), + Subsignal("sda", Pins("L21")), + IOStandard("LVCMOS25")), + + ("serial", 0, + Subsignal("cts", Pins("L27")), + Subsignal("rts", Pins("K23")), + Subsignal("tx", Pins("K24")), + Subsignal("rx", Pins("M19")), + IOStandard("LVCMOS25")), + + ("spiflash", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("U19")), + Subsignal("dq", Pins("P24", "R25", "R20", "R21")), + IOStandard("LVCMOS25") + ), + + ("mmc", 0, + Subsignal("wp", Pins("Y21")), + Subsignal("det", Pins("AA21")), + Subsignal("cmd", Pins("AB22")), + Subsignal("clk", Pins("AB23")), + Subsignal("dat", Pins("AC20 AA23 AA22 AC21")), + IOStandard("LVCMOS25")), + + ("lcd", 0, + Subsignal("db", Pins("AA13 AA10 AA11 Y10")), + Subsignal("e", Pins("AB10")), + Subsignal("rs", Pins("Y11")), + Subsignal("rw", Pins("AB13")), + IOStandard("LVCMOS15")), + + ("rotary", 0, + Subsignal("a", Pins("Y26")), + Subsignal("b", Pins("Y25")), + Subsignal("push", Pins("AA26")), + IOStandard("LVCMOS25")), + + ("hdmi", 0, + Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")), + Subsignal("de", Pins("H17")), + Subsignal("clk", Pins("K18")), + Subsignal("vsync", Pins("H20")), + Subsignal("hsync", Pins("J18")), + Subsignal("int", Pins("AH24")), + Subsignal("spdif", Pins("J17")), + Subsignal("spdif_out", Pins("G20")), + IOStandard("LVCMOS25")), + + ("ddram", 0, + Subsignal("a", Pins( + "AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14", + "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")), + Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15", + "AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18", + "AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19", + "AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15", + "AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6", + "AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1", + "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", + "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), + IOStandard("SSTL15_T_DCI")), + Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + Misc("VCCAUX_IO=HIGH") + ), + + ("eth_clocks", 0, + Subsignal("tx", Pins("M28")), + Subsignal("gtx", Pins("K30")), + Subsignal("rx", Pins("U27")), + IOStandard("LVCMOS25") + ), + ("eth", 0, + Subsignal("rst_n", Pins("L20")), + Subsignal("int_n", Pins("N30")), + Subsignal("mdio", Pins("J21")), + Subsignal("mdc", Pins("R23")), + Subsignal("dv", Pins("R28")), + Subsignal("rx_er", Pins("V26")), + Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")), + Subsignal("tx_en", Pins("M27")), + Subsignal("tx_er", Pins("N29")), + Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")), + Subsignal("col", Pins("W19")), + Subsignal("crs", Pins("R30")), + IOStandard("LVCMOS25") + ), + + ("pcie_x1", 0, + Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), + Subsignal("clk_p", Pins("U8")), + Subsignal("clk_n", Pins("U7")), + Subsignal("rx_p", Pins("M6")), + Subsignal("rx_n", Pins("M5")), + Subsignal("tx_p", Pins("L4")), + Subsignal("tx_n", Pins("L3")) + ), + ("pcie_x2", 0, + Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), + Subsignal("clk_p", Pins("U8")), + Subsignal("clk_n", Pins("U7")), + Subsignal("rx_p", Pins("M6 P6")), + Subsignal("rx_n", Pins("M5 P5")), + Subsignal("tx_p", Pins("L4 M2")), + Subsignal("tx_n", Pins("L3 M1")) + ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), + Subsignal("clk_p", Pins("U8")), + Subsignal("clk_n", Pins("U7")), + Subsignal("rx_p", Pins("M6 P6 R4 T6")), + Subsignal("rx_n", Pins("M5 P5 R3 T5")), + Subsignal("tx_p", Pins("L4 M2 N4 P2")), + Subsignal("tx_n", Pins("L3 M1 N3 P1")) + ), + ("pcie_x8", 0, + Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), + Subsignal("clk_p", Pins("U8")), + Subsignal("clk_n", Pins("U7")), + Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")), + Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")), + Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")), + Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1")) + ) +] + +_connectors = [ + ("HPC", { + "DP1_M2C_P": "D6", + "DP1_M2C_N": "D5", + "DP2_M2C_P": "B6", + "DP2_M2C_N": "B5", + "DP3_M2C_P": "A8", + "DP3_M2C_N": "A7", + "DP1_C2M_P": "C4", + "DP1_C2M_N": "C3", + "DP2_C2M_P": "B2", + "DP2_C2M_N": "B1", + "DP3_C2M_P": "A4", + "DP3_C2M_N": "A3", + "DP0_C2M_P": "D2", + "DP0_C2M_N": "D1", + "DP0_M2C_P": "E4", + "DP0_M2C_N": "E3", + "LA06_P": "H30", + "LA06_N": "G30", + "LA10_P": "D29", + "LA10_N": "C30", + "LA14_P": "B28", + "LA14_N": "A28", + "LA18_CC_P": "F21", + "LA18_CC_N": "E21", + "LA27_P": "C19", + "LA27_N": "B19", + "HA01_CC_P": "H14", + "HA01_CC_N": "G14", + "HA05_P": "F15", + "HA05_N": "E16", + "HA09_P": "F12", + "HA09_N": "E13", + "HA13_P": "L16", + "HA13_N": "K16", + "HA16_P": "L15", + "HA16_N": "K15", + "HA20_P": "K13", + "HA20_N": "J13", + "CLK1_M2C_P": "D17", + "CLK1_M2C_N": "D18", + "LA00_CC_P": "C25", + "LA00_CC_N": "B25", + "LA03_P": "H26", + "LA03_N": "H27", + "LA08_P": "E29", + "LA08_N": "E30", + "LA12_P": "C29", + "LA12_N": "B29", + "LA16_P": "B27", + "LA16_N": "A27", + "LA20_P": "E19", + "LA20_N": "D19", + "LA22_P": "C20", + "LA22_N": "B20", + "LA25_P": "G17", + "LA25_N": "F17", + "LA29_P": "C17", + "LA29_N": "B17", + "LA31_P": "G22", + "LA31_N": "F22", + "LA33_P": "H21", + "LA33_N": "H22", + "HA03_P": "C12", + "HA03_N": "B12", + "HA07_P": "B14", + "HA07_N": "A15", + "HA11_P": "B13", + "HA11_N": "A13", + "HA14_P": "J16", + "HA14_N": "H16", + "HA18_P": "K14", + "HA18_N": "J14", + "HA22_P": "L11", + "HA22_N": "K11", + "GBTCLK1_M2C_P": "E8", + "GBTCLK1_M2C_N": "E7", + "GBTCLK0_M2C_P": "C8", + "GBTCLK0_M2C_N": "C7", + "LA01_CC_P": "D26", + "LA01_CC_N": "C26", + "LA05_P": "G29", + "LA05_N": "F30", + "LA09_P": "B30", + "LA09_N": "A30", + "LA13_P": "A25", + "LA13_N": "A26", + "LA17_CC_P": "F20", + "LA17_CC_N": "E20", + "LA23_P": "B22", + "LA23_N": "A22", + "LA26_P": "B18", + "LA26_N": "A18", + "PG_M2C": "J29", + "HA00_CC_P": "D12", + "HA00_CC_N": "D13", + "HA04_P": "F11", + "HA04_N": "E11", + "HA08_P": "E14", + "HA08_N": "E15", + "HA12_P": "C15", + "HA12_N": "B15", + "HA15_P": "H15", + "HA15_N": "G15", + "HA19_P": "H11", + "HA19_N": "H12", + "PRSNT_M2C_B": "M20", + "CLK0_M2C_P": "D27", + "CLK0_M2C_N": "C27", + "LA02_P": "H24", + "LA02_N": "H25", + "LA04_P": "G28", + "LA04_N": "F28", + "LA07_P": "E28", + "LA07_N": "D28", + "LA11_P": "G27", + "LA11_N": "F27", + "LA15_P": "C24", + "LA15_N": "B24", + "LA19_P": "G18", + "LA19_N": "F18", + "LA21_P": "A20", + "LA21_N": "A21", + "LA24_P": "A16", + "LA24_N": "A17", + "LA28_P": "D16", + "LA28_N": "C16", + "LA30_P": "D22", + "LA30_N": "C22", + "LA32_P": "D21", + "LA32_N": "C21", + "HA02_P": "D11", + "HA02_N": "C11", + "HA06_P": "D14", + "HA06_N": "C14", + "HA10_P": "A11", + "HA10_N": "A12", + "HA17_CC_P": "G13", + "HA17_CC_N": "F13", + "HA21_P": "J11", + "HA21_N": "J12", + "HA23_P": "L12", + "HA23_N": "L13", + } + ), + ("LPC", { + "GBTCLK0_M2C_P": "N8", + "GBTCLK0_M2C_N": "N7", + "LA01_CC_P": "AE23", + "LA01_CC_N": "AF23", + "LA05_P": "AG22", + "LA05_N": "AH22", + "LA09_P": "AK23", + "LA09_N": "AK24", + "LA13_P": "AB24", + "LA13_N": "AC25", + "LA17_CC_P": "AB27", + "LA17_CC_N": "AC27", + "LA23_P": "AH26", + "LA23_N": "AH27", + "LA26_P": "AK29", + "LA26_N": "AK30", + "CLK0_M2C_P": "AF22", + "CLK0_M2C_N": "AG23", + "LA02_P": "AF20", + "LA02_N": "AF21", + "LA04_P": "AH21", + "LA04_N": "AJ21", + "LA07_P": "AG25", + "LA07_N": "AH25", + "LA11_P": "AE25", + "LA11_N": "AF25", + "LA15_P": "AC24", + "LA15_N": "AD24", + "LA19_P": "AJ26", + "LA19_N": "AK26", + "LA21_P": "AG27", + "LA21_N": "AG28", + "LA24_P": "AG30", + "LA24_N": "AH30", + "LA28_P": "AE30", + "LA28_N": "AF30", + "LA30_P": "AB29", + "LA30_N": "AB30", + "LA32_P": "Y30", + "LA32_N": "AA30", + "LA06_P": "AK20", + "LA06_N": "AK21", + "LA10_P": "AJ24", + "LA10_N": "AK25", + "LA14_P": "AD21", + "LA14_N": "AE21", + "LA18_CC_P": "AD27", + "LA18_CC_N": "AD28", + "LA27_P": "AJ28", + "LA27_N": "AJ29", + "CLK1_M2C_P": "AG29", + "CLK1_M2C_N": "AH29", + "LA00_CC_P": "AD23", + "LA00_CC_N": "AE24", + "LA03_P": "AG20", + "LA03_N": "AH20", + "LA08_P": "AJ22", + "LA08_N": "AJ23", + "LA12_P": "AA20", + "LA12_N": "AB20", + "LA16_P": "AC22", + "LA16_N": "AD22", + "LA20_P": "AF26", + "LA20_N": "AF27", + "LA22_P": "AJ27", + "LA22_N": "AK28", + "LA25_P": "AC26", + "LA25_N": "AD26", + "LA29_P": "AE28", + "LA29_N": "AF28", + "LA31_P": "AD29", + "LA31_N": "AE29", + "LA33_P": "AC29", + "LA33_N": "AC30", + } + ) +] + + +class Platform(XilinxPlatform): + identifier = 0x4B37 + default_clk_name = "clk156" + default_clk_period = 6.4 + + def __init__(self, toolchain="vivado", programmer="xc3sprog"): + XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, + toolchain=toolchain) + if toolchain == "ise": + self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" + elif toolchain == "vivado": + self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] + self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + self.programmer = programmer + + def create_programmer(self): + if self.programmer == "xc3sprog": + return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit") + elif self.programmer == "vivado": + return VivadoProgrammer() + elif self.programmer == "impact": + return iMPACT() + else: + raise ValueError("{} programmer is not supported".format(programmer)) + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + try: + self.add_period_constraint(self.lookup_request("clk200").p, 5.0) + except ConstraintError: + pass + try: + self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) + except ConstraintError: + pass + if isinstance(self.toolchain, XilinxISEToolchain): + self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";") + else: + self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]") diff --git a/migen/build/platforms/lx9_microboard.py b/migen/build/platforms/lx9_microboard.py new file mode 100644 index 00000000..fb13b1cb --- /dev/null +++ b/migen/build/platforms/lx9_microboard.py @@ -0,0 +1,131 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_io = [ + ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"), + Misc("PULLDOWN"), Misc("TIG")), + + ("user_led", 0, Pins("P4"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + ("user_led", 1, Pins("L6"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + ("user_led", 2, Pins("F5"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + ("user_led", 3, Pins("C2"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + + ("user_dip", 0, Pins("B3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + ("user_dip", 1, Pins("A3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + ("user_dip", 2, Pins("B4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + ("user_dip", 3, Pins("A4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + + # TI CDCE913 programmable triple-output PLL + ("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz + ("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz + ("clk_y3", 0, Pins("C10"), IOStandard("LVCMOS33")), # default: 100 MHz + + # Maxim DS1088LU oscillator, not populated + ("clk_backup", 0, Pins("R8"), IOStandard("LVCMOS33")), + + # TI CDCE913 PLL I2C control + ("pll", 0, + Subsignal("scl", Pins("P12")), + Subsignal("sda", Pins("U13")), + Misc("PULLUP"), + IOStandard("LVCMOS33")), + + # Micron N25Q128 SPI Flash + ("spiflash", 0, + Subsignal("clk", Pins("R15")), + Subsignal("cs_n", Pins("V3")), + Subsignal("dq", Pins("T13 R13 T14 V14")), + IOStandard("LVCMOS33")), + + # PMOD extension connectors + ("pmod", 0, + Subsignal("d", Pins("F15 F16 C17 C18 F14 G14 D17 D18")), + IOStandard("LVCMOS33")), + ("pmod", 1, + Subsignal("d", Pins("H12 G13 E16 E18 K12 K13 F17 F18")), + IOStandard("LVCMOS33")), + + ("pmod_diff", 0, + Subsignal("io", Pins("F15 C17 F14 D17 H12 E16 K12 F17")), + Subsignal("iob", Pins("F16 C18 G14 D18 G13 E18 K13 F18")), + IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("T7"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("R7"), Misc("PULLUP")), + IOStandard("LVCMOS33")), + + ("ddram_clock", 0, + Subsignal("p", Pins("G3")), + Subsignal("n", Pins("G1")), + IOStandard("MOBILE_DDR")), # actually DIFF_ + + # Micron MT46H32M16LFBF-5 LPDDR + ("ddram", 0, + Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 " + "D2 D1 F4 D3 G6")), + Subsignal("ba", Pins("F2 F1")), + Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 " + "M3 M1 N2 N1 T2 T1 U2 U1")), + Subsignal("cke", Pins("H7")), + Subsignal("we_n", Pins("E3")), + Subsignal("cs_n", Pins("K6")), # NC! + Subsignal("cas_n", Pins("K5")), + Subsignal("ras_n", Pins("L5")), + Subsignal("dm", Pins("K3", "K4")), + Subsignal("dqs", Pins("L4", "P2")), + Subsignal("rzq", Pins("N4")), + IOStandard("MOBILE_DDR")), + + # Nat Semi DP83848J 10/100 Ethernet PHY + # pull-ups on col and rx_data set phy addr to 11111b + # and prevent isolate mode (addr 00000b) + ("eth_clocks", 0, + Subsignal("rx", Pins("L15")), + Subsignal("tx", Pins("H17")), + IOStandard("LVCMOS33")), + + ("eth", 0, + Subsignal("col", Pins("M18"), Misc("PULLUP")), + Subsignal("crs", Pins("N17"), Misc("PULLDOWN")), + Subsignal("mdc", Pins("M16"), Misc("PULLDOWN")), + Subsignal("mdio", Pins("L18"), Misc("PULLUP")), # 1k5 ext PULLUP + Subsignal("rst_n", Pins("T18"), Misc("TIG")), + Subsignal("rx_data", Pins("T17 N16 N15 P18"), Misc("PULLUP")), + Subsignal("dv", Pins("P17"), Misc("PULLDOWN")), # MII + Subsignal("rx_er", Pins("N18"), Misc("PULLUP")), # auto MDIX + Subsignal("tx_data", Pins("K18 K17 J18 J16")), + Subsignal("tx_en", Pins("L17")), + Subsignal("tx_er", Pins("L16")), # NC! + IOStandard("LVCMOS33")), + ] + + +class Platform(XilinxPlatform): + default_clk_name = "clk_y3" + default_clk_period = 10 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io) + self.add_platform_command(""" +CONFIG VCCAUX = "3.3"; +""") + self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4" + self.toolchain.ise_commands = """ +promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit +""" + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + + try: + eth_clocks = self.lookup_request("eth_clocks") + self.add_period_constraint(eth_clocks.rx, 40) + self.add_period_constraint(eth_clocks.tx, 40) + self.add_platform_command(""" +TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; +TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; +""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) + except ConstraintError: + pass diff --git a/migen/build/platforms/m1.py b/migen/build/platforms/m1.py new file mode 100644 index 00000000..65216c88 --- /dev/null +++ b/migen/build/platforms/m1.py @@ -0,0 +1,152 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform +from migen.build.xilinx.programmer import UrJTAG + + +_io = [ + ("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + ("user_led", 1, Pins("A16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + + ("user_btn", 0, Pins("AB4"), IOStandard("LVCMOS33")), + ("user_btn", 1, Pins("AA4"), IOStandard("LVCMOS33")), + ("user_btn", 2, Pins("AB5"), IOStandard("LVCMOS33")), + + ("clk50", 0, Pins("AB11"), IOStandard("LVCMOS33")), + + # When executing softcore code in-place from the flash, we want + # the flash reset to be released before the system reset. + ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), + ("norflash", 0, + Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22", + "F21 K17 J17 E22 E20 H18 H19 F20", + "G19 C22 C20 D22 D21 F19 F18 D20 D19")), + Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7", + "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")), + Subsignal("oe_n", Pins("M22")), + Subsignal("we_n", Pins("N20")), + Subsignal("ce_n", Pins("M21")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8) + ), + + ("serial", 0, + Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")) + ), + + ("ddram_clock", 0, + Subsignal("p", Pins("M3")), + Subsignal("n", Pins("L4")), + IOStandard("SSTL2_I") + ), + ("ddram", 0, + Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")), + Subsignal("ba", Pins("A2 E6")), + Subsignal("cs_n", Pins("F7")), + Subsignal("cke", Pins("G7")), + Subsignal("ras_n", Pins("E5")), + Subsignal("cas_n", Pins("C4")), + Subsignal("we_n", Pins("D3")), + Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3", + "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4", + "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")), + Subsignal("dm", Pins("E1 E3 F3 G4")), + Subsignal("dqs", Pins("F1 F2 H5 H6")), + IOStandard("SSTL2_I") + ), + + ("eth_clocks", 0, + Subsignal("phy", Pins("M20")), + Subsignal("rx", Pins("H22")), + Subsignal("tx", Pins("H21")), + IOStandard("LVCMOS33") + ), + ("eth", 0, + Subsignal("rst_n", Pins("R22")), + Subsignal("dv", Pins("V21")), + Subsignal("rx_er", Pins("V22")), + Subsignal("rx_data", Pins("U22 U20 T22 T21")), + Subsignal("tx_en", Pins("N19")), + Subsignal("tx_er", Pins("M19")), + Subsignal("tx_data", Pins("M16 L15 P19 P20")), + Subsignal("col", Pins("W20")), + Subsignal("crs", Pins("W22")), + IOStandard("LVCMOS33") + ), + + ("vga_out", 0, + Subsignal("clk", Pins("A11")), + Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), + Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), + Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")), + Subsignal("hsync_n", Pins("A14")), + Subsignal("vsync_n", Pins("C15")), + Subsignal("psave_n", Pins("B14")), + IOStandard("LVCMOS33") + ), + + ("mmc", 0, + Subsignal("clk", Pins("A10")), + Subsignal("cmd", Pins("B18")), + Subsignal("dat", Pins("A18 E16 C17 A17")), + IOStandard("LVCMOS33") + ), + + # Digital video mixer extension board + ("dvi_in", 0, + Subsignal("clk", Pins("A20")), + Subsignal("data0_n", Pins("A21")), + Subsignal("data1", Pins("B21")), + Subsignal("data2_n", Pins("B22")), + Subsignal("scl", Pins("G16")), + Subsignal("sda", Pins("G17")), + IOStandard("LVCMOS33") + ), + ("dvi_in", 1, + Subsignal("clk", Pins("H17")), + Subsignal("data0_n", Pins("H16")), + Subsignal("data1", Pins("F17")), + Subsignal("data2_n", Pins("F16")), + Subsignal("scl", Pins("J16")), + Subsignal("sda", Pins("K16")), + IOStandard("LVCMOS33") + ), + ("dvi_pots", 0, + Subsignal("charge", Pins("A18")), # SD_DAT0 + Subsignal("blackout", Pins("C17")), # SD_DAT2 + Subsignal("crossfade", Pins("A17")), # SD_DAT3 + IOStandard("LVCMOS33") + ) +] + + +class Platform(XilinxPlatform): + identifier = 0x4D31 + default_clk_name = "clk50" + default_clk_period = 20 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io) + + def create_programmer(self): + return UrJTAG(cable="milkymist", flash_proxy_basename="fjmem-m1.bit") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + + try: + eth_clocks = self.lookup_request("eth_clocks") + self.add_period_constraint(eth_clocks.rx, 40) + self.add_period_constraint(eth_clocks.tx, 40) + self.add_platform_command(""" +TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; +TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; +""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) + except ConstraintError: + pass + + for i in range(2): + si = "dviclk"+str(i) + try: + self.add_period_constraint(self.lookup_request("dvi_in", i).clk, 26.7) + except ConstraintError: + pass diff --git a/migen/build/platforms/mercury.py b/migen/build/platforms/mercury.py new file mode 100644 index 00000000..699218df --- /dev/null +++ b/migen/build/platforms/mercury.py @@ -0,0 +1,138 @@ +# This file is Copyright (c) 2015 William D. Jones +# License: BSD + +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform +from migen.build.xilinx.programmer import XC3SProg + + +_io = [ + ("clk50", 0, Pins("P43"), IOStandard("LVCMOS33")), + + ("user_btn", 0, Pins("P41"), IOStandard("LVTTL")), + + # The serial interface and flash memory have a shared SPI bus. + # FPGA is secondary + ("spiserial", 0, + Subsignal("cs_n", Pins("P39"), IOStandard("LVTTL")), + Subsignal("clk", Pins("P53"), IOStandard("LVTTL")), + Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")), + Subsignal("miso", Pins("P51"), IOStandard("LVTTL")) + ), + + # FPGA is primary + ("spiflash", 0, + Subsignal("cs_n", Pins("P27"), IOStandard("LVTTL")), + Subsignal("clk", Pins("P53"), IOStandard("LVTTL")), + Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")), + Subsignal("miso", Pins("P51"), IOStandard("LVTTL")) + ), + + ("spiflash2x", 0, + Subsignal("cs_n", Pins("P27")), + Subsignal("clk", Pins("P53")), + Subsignal("dq", Pins("P46", "P51")), + IOStandard("LVTTL"), Misc("SLEW=FAST") + ), + + # ADC over SPI- FPGA is primary + ("adc", 0, + Subsignal("cs_n", Pins("P12"), IOStandard("LVTTL")), + Subsignal("clk", Pins("P9"), IOStandard("LVTTL")), + Subsignal("mosi", Pins("P10"), IOStandard("LVTTL")), + Subsignal("miso", Pins("P21"), IOStandard("LVTTL")) + ), + + # GPIO control- SRAM and connectors are shared: these pins control how + # to access each. Recommended to combine with gpio_sram_bus extension, + # since these pins are related but not exposed on connectors. + ("gpio_ctl", 0, + Subsignal("ce_n", Pins("P3")), # Memory chip-enable. Called MEM_CEN + # in schematic. + Subsignal("bussw_oe_n", Pins("P30")), # 5V tolerant GPIO is shared + # w/ memory using this pin. + IOStandard("LVTTL"), Misc("SLEW=FAST") + ) +] + +# Perhaps define some connectors as having a specific purpose- i.e. a 5V GPIO +# bus with data, peripheral-select, and control signals? +_connectors = [ + ("GPIO", """P59 P60 P61 P62 P64 P57 + P56 P52 P50 P49 P85 P84 + P83 P78 P77 P65 P70 P71 + P72 P73 P5 P4 P6 P98 + P94 P93 P90 P89 P88 P86"""), # 5V I/O- LVTTL + ("DIO", "P20 P32 P33 P34 P35 P36 P37"), # Fast 3.3V IO (Directly attached + # to FPGA)- LVCMOS33 + ("CLKIO", "P40 P44"), # Clock IO (Can be used as GPIO)- LVCMOS33 + ("INPUT", "P68 P97 P7 P82"), # Input-only pins- LVCMOS33 + ("LED", "P13 P15 P16 P19") # LEDs can be used as pins as well- LVTTL. +] + +# Some default useful extensions- use platform.add_extension() to use, e.g. +# from migen.build.platforms import mercury +# plat = mercury.Platform() +# plat.add_extension(mercury.gpio_sram) + +# SRAM and 5V-tolerant I/O share a parallel bus on 200k gate version. The SRAM +# controller needs to take care of switching the bus between the two. Meant to +# be Cat() into one GPIO bus, and combined with gpio_ctl. +gpio_sram = [ + ("gpio_sram_bus", 0, + Subsignal("a", Pins("""GPIO:0 GPIO:1 GPIO:2 GPIO:3 + GPIO:4 GPIO:5 GPIO:6 GPIO:7 + GPIO:8 GPIO:9 GPIO:10 GPIO:11 + GPIO:12 GPIO:13 GPIO:14 GPIO:15 + GPIO:16 GPIO:17 GPIO:18 GPIO:19""")), + # A19 is actually unused- free for GPIO + # 8-bit data bus + Subsignal("d", Pins("""GPIO:20 GPIO:21 GPIO:22 GPIO:23 + GPIO:24 GPIO:25 GPIO:26 GPIO:27""")), + Subsignal("we_n", Pins("GPIO:28")), + Subsignal("unused", Pins("GPIO:29")), # Only used by GPIO. + # Subsignal("oe_n", Pins()), # If OE wasn't tied to ground on Mercury, + # this pin would be here. + IOStandard("LVTTL"), Misc("SLEW=FAST") + ) +] + +# The "serial port" is in fact over SPI. The creators of the board provide a +# VHDL file for talking over this interface. In light of space constraints and +# the fact that both the FT245RL and FPGA can BOTH be SPI primaries, however, +# it may be necessary to sacrifice two "high-speed" (DIO, INPUT) pins instead. +serial = [ + ("serial", 0, + Subsignal("tx", Pins("DIO:0"), IOStandard("LVCMOS33")), # FTDI D1 + Subsignal("rx", Pins("INPUT:0"), IOStandard("LVCMOS33")) + ) # FTDI D0 +] + +leds = [ + ("user_led", 0, Pins("LED:0"), IOStandard("LVTTL")), + ("user_led", 1, Pins("LED:1"), IOStandard("LVTTL")), + ("user_led", 2, Pins("LED:2"), IOStandard("LVTTL")), + ("user_led", 3, Pins("LED:3"), IOStandard("LVTTL")) +] + +# See: http://www.micro-nova.com/mercury-baseboard/ +# Not implemented yet. +baseboard = [ +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk50" + default_clk_period = 20 + + def __init__(self, device="xc3s200a-4-vq100"): + XilinxPlatform.__init__(self, device, _io, _connectors) + # Small device- optimize for AREA instead of SPEED (LM32 runs at about + # 60-65MHz in AREA configuration). + self.toolchain.xst_opt = """-ifmt MIXED +-use_new_parser yes +-opt_mode AREA +-register_balancing yes""" + + def create_programmer(self): + raise NotImplementedError diff --git a/migen/build/platforms/mimasv2.py b/migen/build/platforms/mimasv2.py new file mode 100644 index 00000000..703fdc49 --- /dev/null +++ b/migen/build/platforms/mimasv2.py @@ -0,0 +1,124 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_io = [ + ("clk100", 0, Pins("V10"), IOStandard("LVCMOS33")), + ("clk12", 0, Pins("D9"), IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("A8"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("rx", Pins("B8"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST"))), + + ("spiflash", 0, + Subsignal("cs_n", Pins("V3")), + Subsignal("clk", Pins("R15")), + Subsignal("mosi", Pins("T13")), + Subsignal("miso", Pins("R13"), Misc("PULLUP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + + ("ddram_clock", 0, + Subsignal("p", Pins("G3")), + Subsignal("n", Pins("G1")), + IOStandard("MOBILE_DDR")), + + ("ddram", 0, + Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")), + Subsignal("ba", Pins("F2 F1")), + Subsignal("cke", Pins("H7")), + Subsignal("ras_n", Pins("L5")), + Subsignal("cas_n", Pins("K5")), + Subsignal("we_n", Pins("E3")), + Subsignal( + "dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1") + ), + Subsignal("dqs", Pins("L4 P2")), + Subsignal("dm", Pins("K3 K4")), + IOStandard("MOBILE_DDR")), + + ("dipswitch", 0, Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 1, Pins("C18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 2, Pins("D17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 3, Pins("D18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 4, Pins("E18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 5, Pins("E16"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 6, Pins("F18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 7, Pins("F17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + + ("buttonswitch", 0, Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 1, Pins("K17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 2, Pins("L17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 3, Pins("M16"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 4, Pins("L18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 5, Pins("M18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + + ("user_led", 0, Pins("T18"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 1, Pins("T17"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 3, Pins("U17"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 4, Pins("N16"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 5, Pins("N15"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 6, Pins("P16"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 7, Pins("P15"), IOStandard("LVCMOS33"), Drive(8)), + + ("mmc", 0, + Subsignal("dat", Pins("K14 G18 J13 L13"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + + Subsignal("cmd", Pins("G16"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + + Subsignal("clk", Pins("L12"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST"))), + + ("sevenseg", 0, + Subsignal("segment7", Pins("A3"), IOStandard("LVCMOS33")), # A + Subsignal("segment6", Pins("B4"), IOStandard("LVCMOS33")), # B + Subsignal("segment5", Pins("A4"), IOStandard("LVCMOS33")), # C + Subsignal("segment4", Pins("C4"), IOStandard("LVCMOS33")), # D + Subsignal("segment3", Pins("C5"), IOStandard("LVCMOS33")), # E + Subsignal("segment2", Pins("D6"), IOStandard("LVCMOS33")), # F + Subsignal("segment1", Pins("C6"), IOStandard("LVCMOS33")), # G + Subsignal("segment0", Pins("A5"), IOStandard("LVCMOS33")), # Dot + Subsignal("enable0", Pins("B2"), IOStandard("LVCMOS33")), # EN0 + Subsignal("enable1", Pins("A2"), IOStandard("LVCMOS33")), # EN1 + Subsignal("enable2", Pins("B3"), IOStandard("LVCMOS33"))), # EN2 + + + ("audio", 0, + Subsignal("channel1", Pins("B16"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("channel2", Pins("A16"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST"))), + + ("vga_out", 0, + Subsignal("hsync_n", Pins("B12"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("vsync_n", Pins("A12"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("r", Pins("A9 B9 C9"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("g", Pins("C10 A10 C11"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("b", Pins("B11 A11"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST"))) +] + +_connectors = [ + ("P6", "T3 R3 V5 U5 V4 T4 V7 U7"), + ("P7", "V11 U11 V13 U13 T10 R10 T11 R11"), + ("P8", "L16 L15 K16 K15 J18 J16 H18 H17") +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 10 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx9-csg324-2", _io, _connectors) + + def create_programmer(self): + raise NotImplementedError diff --git a/migen/build/platforms/minispartan6.py b/migen/build/platforms/minispartan6.py new file mode 100644 index 00000000..c46fa29c --- /dev/null +++ b/migen/build/platforms/minispartan6.py @@ -0,0 +1,126 @@ +# This file is Copyright (c) 2015 Matt O'Gorman +# License: BSD + +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform +from migen.build.xilinx.programmer import XC3SProg, FpgaProg + + +_io = [ + ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("N9"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("M9"), IOStandard("LVCMOS33")), + ("user_led", 3, Pins("P9"), IOStandard("LVCMOS33")), + ("user_led", 4, Pins("T8"), IOStandard("LVCMOS33")), + ("user_led", 5, Pins("N8"), IOStandard("LVCMOS33")), + ("user_led", 6, Pins("P8"), IOStandard("LVCMOS33")), + ("user_led", 7, Pins("P7"), IOStandard("LVCMOS33")), + + ("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")), + + ("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")), + ("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")), + + ("spiflash", 0, + Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")), + Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")), + Subsignal("mosi", Pins("T10"), IOStandard("LVCMOS33")), + Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33")) + ), + + ("adc", 0, + Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")), + Subsignal("clk", Pins("G6"), IOStandard("LVCMOS33")), + Subsignal("mosi", Pins("H4"), IOStandard("LVCMOS33")), + Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33")) + ), + + ("serial", 0, + Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1 + Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0 + ), + + ("audio", 0, + Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")), + Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33")) + ), + + ("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + ("sdram", 0, + Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")), + Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")), + Subsignal("we_n", Pins("R5")), + Subsignal("ras_n", Pins("R2")), + Subsignal("cas_n", Pins("T4")), + Subsignal("cs_n", Pins("R1")), + Subsignal("cke", Pins("H16")), + Subsignal("ba", Pins("R14 T14")), + Subsignal("dm", Pins("T5 F15")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + + ("usb_fifo", 0, + Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")), + Subsignal("rxf_n", Pins("N3")), + Subsignal("txe_n", Pins("N1")), + Subsignal("rd_n", Pins("M1")), + Subsignal("wr_n", Pins("M2")), + Subsignal("siwua", Pins("M3")), + IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST") + ), + + ("sd", 0, + Subsignal("sck", Pins("L12")), + Subsignal("d3", Pins("K12")), + Subsignal("d", Pins("M10")), + Subsignal("d1", Pins("L10")), + Subsignal("d2", Pins("J11")), + Subsignal("cmd", Pins("K11")), + IOStandard("LVCMOS33") + ), + + ("dvi_in", 0, + Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")), + Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")), + Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33")) + ), + + ("dvi_out", 0, + Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")), + Subsignal("data_p", Pins("C13 B12 C11"), IOStandard("TMDS_33")), + Subsignal("data_n", Pins("A13 A12 A11"), IOStandard("TMDS_33")), + ) +] + +_connectors = [ + ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"), + ("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"), + ("C", "J13 J12 K14 L14 L13 M14 M13 N14 M12 N12 P12 M11"), + ("D", "D6 C6 E6 C5"), + ("E", "D5 A4 G5 A3 B3 A2 B2 C3 C2 D3 D1 E3"), + ("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1") +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk32" + default_clk_period = 31.25 + + def __init__(self, device="xc6slx9", programmer="xc3sprog"): + self.programmer = programmer + XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) + + def create_programmer(self): + if self.programmer == "xc3sprog": + return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit") + elif self.programmer == "fpgaprog": + return FpgaProg() + else: + raise ValueError("{} programmer is not supported".format(programmer)) diff --git a/migen/build/platforms/mixxeo.py b/migen/build/platforms/mixxeo.py new file mode 100644 index 00000000..8d4c85d8 --- /dev/null +++ b/migen/build/platforms/mixxeo.py @@ -0,0 +1,188 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform +from migen.build.xilinx.programmer import UrJTAG + + +_io = [ + ("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + + ("clk50", 0, Pins("AB13"), IOStandard("LVCMOS33")), + + # When executing softcore code in-place from the flash, we want + # the flash reset to be released before the system reset. + ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), + ("norflash", 0, + Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22", + "F21 K17 J17 E22 E20 H18 H19 F20", + "G19 C22 C20 D22 D21 F19 F18 D20 D19")), + Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7", + "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")), + Subsignal("oe_n", Pins("M22")), + Subsignal("we_n", Pins("N20")), + Subsignal("ce_n", Pins("M21")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8) + ), + + ("serial", 0, + Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")) + ), + + ("ddram_clock", 0, + Subsignal("p", Pins("M3")), + Subsignal("n", Pins("L4")), + IOStandard("SSTL2_I") + ), + ("ddram", 0, + Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")), + Subsignal("ba", Pins("A2 E6")), + Subsignal("cs_n", Pins("F7")), + Subsignal("cke", Pins("G7")), + Subsignal("ras_n", Pins("E5")), + Subsignal("cas_n", Pins("C4")), + Subsignal("we_n", Pins("D3")), + Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3", + "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4", + "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")), + Subsignal("dm", Pins("E1 E3 F3 G4")), + Subsignal("dqs", Pins("F1 F2 H5 H6")), + IOStandard("SSTL2_I") + ), + + ("eth_clocks", 0, + Subsignal("phy", Pins("M20")), + Subsignal("rx", Pins("H22")), + Subsignal("tx", Pins("H21")), + IOStandard("LVCMOS33") + ), + ("eth", 0, + Subsignal("rst_n", Pins("R22")), + Subsignal("dv", Pins("V21")), + Subsignal("rx_er", Pins("V22")), + Subsignal("rx_data", Pins("U22 U20 T22 T21")), + Subsignal("tx_en", Pins("N19")), + Subsignal("tx_er", Pins("M19")), + Subsignal("tx_data", Pins("M16 L15 P19 P20")), + Subsignal("col", Pins("W20")), + Subsignal("crs", Pins("W22")), + IOStandard("LVCMOS33") + ), + + ("vga_out", 0, + Subsignal("clk", Pins("A10")), + Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), + Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), + Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")), + Subsignal("hsync_n", Pins("A14")), + Subsignal("vsync_n", Pins("C15")), + Subsignal("psave_n", Pins("B14")), + IOStandard("LVCMOS33") + ), + ("dvi_out", 0, + Subsignal("clk_p", Pins("W12"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("Y12"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("Y16"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("W15"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("AA16"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("AB16"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("Y15"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("AB15"), IOStandard("TMDS_33")), + ), + + ("mmc", 0, + Subsignal("clk", Pins("J3")), + Subsignal("cmd", Pins("K1")), + Subsignal("dat", Pins("J6 K6 N1 K5")), + IOStandard("LVCMOS33") + ), + + ("dvi_in", 0, + Subsignal("clk_p", Pins("K20"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("K19"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("B21"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("B22"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("A20"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("A21"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("K16"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("J16"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("G20"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("H16"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 1, + Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A11"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("B18"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("A18"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("C17"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("A17"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("F17"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("F16"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 2, + Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("AB11"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("V11"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("W11"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("AA10"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("AB10"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("R11"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("T11"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("C16"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("B16"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("D6"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("A4"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 3, + Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("J22"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("P18"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("R19"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("P17"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("N16"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("M17"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("M18"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("P21"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("N22"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("H17"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("C19"), IOStandard("LVCMOS33")) + ), +] + + +class Platform(XilinxPlatform): + identifier = 0x4D58 + default_clk_name = "clk50" + default_clk_period = 20 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io) + self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") + + def create_programmer(self): + return UrJTAG("fjmem-mixxeo.bit") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + + try: + eth_clocks = self.lookup_request("eth_clocks") + self.add_period_constraint(eth_clocks.rx, 40) + self.add_period_constraint(eth_clocks.tx, 40) + self.add_platform_command(""" +TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; +TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; +""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) + except ConstraintError: + pass + + for i in range(4): + try: + self.add_period_constraint(self.lookup_request("dvi_in", i).clk_p, 12) + except ConstraintError: + pass diff --git a/migen/build/platforms/ml605.py b/migen/build/platforms/ml605.py new file mode 100644 index 00000000..04184b74 --- /dev/null +++ b/migen/build/platforms/ml605.py @@ -0,0 +1,60 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_io = [ + # System clock (Differential 200MHz) + ("clk200", 0, + Subsignal("p", Pins("J9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("n", Pins("H9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")) + ), + + # User clock (66MHz) + ("clk66", 0, Pins("U23"), IOStandard("LVCMOS25")), + + # CPU reset switch + ("cpu_reset", 0, Pins("H10"), IOStandard("SSTL15")), + + # LEDs + ("user_led", 0, Pins("AC22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 1, Pins("AC24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 2, Pins("AE22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 3, Pins("AE23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 4, Pins("AB23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 5, Pins("AG23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 6, Pins("AE24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 7, Pins("AD24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + + # USB-to-UART + ("serial", 0, + Subsignal("tx", Pins("J25"), IOStandard("LVCMOS25")), + Subsignal("rx", Pins("J24"), IOStandard("LVCMOS25")) + ), + + # 10/100/1000 Tri-Speed Ethernet PHY + ("eth_clocks", 0, + Subsignal("rx", Pins("AP11")), + Subsignal("tx", Pins("AD12")), + IOStandard("LVCMOS25") + ), + ("eth", 0, + Subsignal("rst_n", Pins("AH13")), + Subsignal("dv", Pins("AM13")), + Subsignal("rx_er", Pins("AG12")), + Subsignal("rx_data", Pins("AN13 AF14 AE14 AN12 AM12 AD11 AC12 AC13")), + Subsignal("tx_en", Pins("AJ10")), + Subsignal("tx_er", Pins("AH10")), + Subsignal("tx_data", Pins("AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11")), + Subsignal("col", Pins("AK13")), + Subsignal("crs", Pins("AL13")), + IOStandard("LVCMOS25") + ) +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk200" + default_clk_period = 5 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io) diff --git a/migen/build/platforms/papilio_pro.py b/migen/build/platforms/papilio_pro.py new file mode 100644 index 00000000..8ee33005 --- /dev/null +++ b/migen/build/platforms/papilio_pro.py @@ -0,0 +1,62 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform +from migen.build.xilinx.programmer import XC3SProg + + +_io = [ + ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + + ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP")) + ), + + ("spiflash", 0, + Subsignal("cs_n", Pins("P38")), + Subsignal("clk", Pins("P70")), + Subsignal("mosi", Pins("P64")), + Subsignal("miso", Pins("P65"), Misc("PULLUP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + ("spiflash2x", 0, + Subsignal("cs_n", Pins("P38")), + Subsignal("clk", Pins("P70")), + Subsignal("dq", Pins("P64", "P65")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + + ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + ("sdram", 0, + Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44", + "P43 P41 P40 P141 P35 P34")), + Subsignal("ba", Pins("P143 P142")), + Subsignal("cs_n", Pins("P1")), + Subsignal("cke", Pins("P33")), + Subsignal("ras_n", Pins("P2")), + Subsignal("cas_n", Pins("P5")), + Subsignal("we_n", Pins("P6")), + Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")), + Subsignal("dm", Pins("P7 P17")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ) +] + +_connectors = [ + ("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"), + ("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"), + ("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134") +] + + +class Platform(XilinxPlatform): + identifier = 0x5050 + default_clk_name = "clk32" + default_clk_period = 31.25 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors) + + def create_programmer(self): + return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit") diff --git a/migen/build/platforms/pipistrello.py b/migen/build/platforms/pipistrello.py new file mode 100644 index 00000000..c202556a --- /dev/null +++ b/migen/build/platforms/pipistrello.py @@ -0,0 +1,138 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform +from migen.build.xilinx.programmer import XC3SProg + + +_io = [ + ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi + ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi + ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd + ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd + ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb + + ("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")), + + ("clk50", 0, Pins("H17"), IOStandard("LVTTL")), + + ("serial", 0, + Subsignal("tx", Pins("A10")), + Subsignal("rx", Pins("A11"), Misc("PULLUP")), + Subsignal("cts", Pins("C10"), Misc("PULLUP")), + Subsignal("rts", Pins("A9"), Misc("PULLUP")), + IOStandard("LVTTL"), + ), + + ("usb_fifo", 0, + Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")), + Subsignal("rxf_n", Pins("C7")), + Subsignal("txe_n", Pins("A6")), + Subsignal("rd_n", Pins("B6")), + Subsignal("wr_n", Pins("A5")), + Subsignal("siwua", Pins("C5")), + IOStandard("LVTTL"), + ), + + ("hdmi", 0, + Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("T6"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("V6"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("U7"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("V7"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("U8"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("V8"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("V9"), IOStandard("I2C")), + Subsignal("sda", Pins("T9"), IOStandard("I2C")), + Subsignal("hpd_notif", Pins("R8"), IOStandard("LVTTL")), + ), + + ("spiflash", 0, + Subsignal("cs_n", Pins("V3")), + Subsignal("clk", Pins("R15")), + Subsignal("mosi", Pins("T13")), + Subsignal("miso", Pins("R13"), Misc("PULLUP")), + Subsignal("wp", Pins("T14")), + Subsignal("hold", Pins("V14")), + IOStandard("LVTTL"), Misc("SLEW=FAST") + ), + + ("spiflash2x", 0, + Subsignal("cs_n", Pins("V3")), + Subsignal("clk", Pins("R15")), + Subsignal("dq", Pins("T13 R13"), Misc("PULLUP")), + Subsignal("wp", Pins("T14")), + Subsignal("hold", Pins("V14")), + IOStandard("LVTTL"), Misc("SLEW=FAST") + ), + + ("spiflash4x", 0, + Subsignal("cs_n", Pins("V3")), + Subsignal("clk", Pins("R15")), + Subsignal("dq", Pins("T13 R13 T14 V14"), Misc("PULLUP")), + IOStandard("LVTTL"), Misc("SLEW=FAST") + ), + + ("mmc", 0, + Subsignal("clk", Pins("A3")), + Subsignal("cmd", Pins("B3"), Misc("PULLUP")), + Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")), + IOStandard("SDIO") + ), + + ("mmc_spi", 0, + Subsignal("cs_n", Pins("A2"), Misc("PULLUP")), + Subsignal("clk", Pins("A3")), + Subsignal("mosi", Pins("B3")), + Subsignal("miso", Pins("B4"), Misc("PULLUP")), + IOStandard("SDIO") + ), + + ("audio", 0, + Subsignal("l", Pins("R7"), Misc("SLEW=SLOW")), + Subsignal("r", Pins("T7"), Misc("SLEW=SLOW")), + IOStandard("LVTTL"), + ), + + ("pmod", 0, + Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")), + IOStandard("LVTTL") + ), + + ("ddram_clock", 0, + Subsignal("p", Pins("G3")), + Subsignal("n", Pins("G1")), + IOStandard("MOBILE_DDR") + ), + + ("ddram", 0, + Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")), + Subsignal("ba", Pins("F2 F1")), + Subsignal("cke", Pins("H7")), + Subsignal("ras_n", Pins("L5")), + Subsignal("cas_n", Pins("K5")), + Subsignal("we_n", Pins("E3")), + Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")), + Subsignal("dqs", Pins("L4 P2")), + Subsignal("dm", Pins("K3 K4")), + IOStandard("MOBILE_DDR") + ) +] + +_connectors = [ + ("A", "U18 T17 P17 P16 N16 N17 M16 L15 L17 K15 K17 J16 H15 H18 F18 D18"), + ("B", "C18 E18 G18 H16 J18 K18 K16 L18 L16 M18 N18 N15 P15 P18 T18 U17"), + ("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"), +] + + +class Platform(XilinxPlatform): + identifier = 0x5049 + default_clk_name = "clk50" + default_clk_period = 20 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors) + self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6" + + def create_programmer(self): + return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit") diff --git a/migen/build/platforms/rhino.py b/migen/build/platforms/rhino.py new file mode 100644 index 00000000..0cb99596 --- /dev/null +++ b/migen/build/platforms/rhino.py @@ -0,0 +1,142 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_io = [ + ("user_led", 0, Pins("Y3")), + ("user_led", 1, Pins("Y1")), + ("user_led", 2, Pins("W2")), + ("user_led", 3, Pins("W1")), + ("user_led", 4, Pins("V3")), + ("user_led", 5, Pins("V1")), + ("user_led", 6, Pins("U2")), + ("user_led", 7, Pins("U1")), + + ("clk100", 0, + Subsignal("p", Pins("B14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("n", Pins("A14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")) + ), + + ("gpio", 0, Pins("R8")), + + ("gpmc", 0, + Subsignal("clk", Pins("R26")), + Subsignal("a", Pins("N17 N18 L23 L24 N19 N20 N21 N22 P17 P19")), + Subsignal("d", Pins("N23 N24 R18 R19 P21 P22 R20 R21 P24 P26 R23 R24 T22 T23 U23 R25")), + Subsignal("we_n", Pins("W26")), + Subsignal("oe_n", Pins("AA25")), + Subsignal("ale_n", Pins("AA26")), + Subsignal("wait", Pins("AD26")), # WAIT1/BUSY0 + IOStandard("LVCMOS33")), + # Warning: CS are numbered 1-7 on ARM side and 0-6 on FPGA side. + # Numbers here are given on the FPGA side. + ("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")), # nCS0 + ("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")), # nCS1 + ("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")), # nCS6 + ("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")), # nCS2 + ("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")), # nCS3 + ("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")), # nCS4 + ("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")), # nCS5 + + # FMC150 + ("fmc150_ctrl", 0, + Subsignal("spi_sclk", Pins("AE5")), + Subsignal("spi_data", Pins("AF5")), + + Subsignal("adc_sdo", Pins("U13")), + Subsignal("adc_en_n", Pins("AA15")), + Subsignal("adc_reset", Pins("V13")), + + Subsignal("cdce_sdo", Pins("AA8")), + Subsignal("cdce_en_n", Pins("Y9")), + Subsignal("cdce_reset_n", Pins("AB7")), + Subsignal("cdce_pd_n", Pins("AC6")), + Subsignal("cdce_pll_status", Pins("W7")), + Subsignal("cdce_ref_en", Pins("W8")), + + Subsignal("dac_sdo", Pins("W9")), + Subsignal("dac_en_n", Pins("W10")), + + Subsignal("mon_sdo", Pins("AC5")), + Subsignal("mon_en_n", Pins("AD6")), + Subsignal("mon_reset_n", Pins("AF6")), + Subsignal("mon_int_n", Pins("AD5")), + + Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33")) + ), + ("ti_dac", 0, # DAC3283 + Subsignal("dat_p", Pins("AA10 AA9 V11 Y11 W14 Y12 AD14 AE13"), IOStandard("LVDS_25")), + Subsignal("dat_n", Pins("AB11 AB9 V10 AA11 Y13 AA12 AF14 AF13"), IOStandard("LVDS_25")), + Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")), + Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")), + Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25")) + ), + ("ti_adc", 0, # ADS62P49 + Subsignal("dat_a_p", Pins("AB14 Y21 W20 AB22 V18 W17 AA21")), + Subsignal("dat_a_n", Pins("AC14 AA22 Y20 AC22 W19 W18 AB21")), + Subsignal("dat_b_p", Pins("Y17 U15 AA19 W16 AA18 Y15 V14")), + Subsignal("dat_b_n", Pins("AA17 V16 AB19 Y16 AB17 AA16 V15")), + IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE") + ), + ("fmc150_clocks", 0, + Subsignal("dac_clk_p", Pins("V12"), IOStandard("LVDS_25")), + Subsignal("dac_clk_n", Pins("W12"), IOStandard("LVDS_25")), + Subsignal("adc_clk_p", Pins("AE15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("adc_clk_n", Pins("AF15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("clk_to_fpga", Pins("W24"), IOStandard("LVCMOS25")) + ), + + ("fmc150_ext_trigger", 0, Pins("U26")), + + # Vermeer radar testbed + # Switch controller + ("pca9555", 0, + Subsignal("sda", Pins("C13")), + Subsignal("scl", Pins("G8")), + IOStandard("LVCMOS33") + ), + # TX path + ("pe43602", 0, + Subsignal("d", Pins("H8")), + Subsignal("clk", Pins("B3")), + Subsignal("le", Pins("F7")), + IOStandard("LVCMOS33") + ), + ("rfmd2081", 0, + Subsignal("enx", Pins("E5")), + Subsignal("sclk", Pins("G6")), + Subsignal("sdata", Pins("F5")), + Subsignal("locked", Pins("E6")), + IOStandard("LVCMOS33") + ), + # RX path + ("lmh6521", 0, + Subsignal("scsb", Pins("C5")), + Subsignal("sclk", Pins("G10")), + Subsignal("sdi", Pins("D5")), + Subsignal("sdo", Pins("F9")), + IOStandard("LVCMOS33") + ), + ("lmh6521", 1, + Subsignal("scsb", Pins("E10")), + Subsignal("sclk", Pins("A4")), + Subsignal("sdi", Pins("B4")), + Subsignal("sdo", Pins("H10")), + IOStandard("LVCMOS33") + ), + ("rffc5071", 0, + Subsignal("enx", Pins("A2")), + Subsignal("sclk", Pins("G9")), + Subsignal("sdata", Pins("H9")), + Subsignal("locked", Pins("A3")), + IOStandard("LVCMOS33") + ) +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 10 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io) diff --git a/migen/build/platforms/roach.py b/migen/build/platforms/roach.py new file mode 100644 index 00000000..19c1ccb4 --- /dev/null +++ b/migen/build/platforms/roach.py @@ -0,0 +1,35 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_io = [ + ("epb", 0, + Subsignal("cs_n", Pins("K13")), + Subsignal("r_w_n", Pins("AF20")), + Subsignal("be_n", Pins("AF14 AF18")), + Subsignal("oe_n", Pins("AF21")), + Subsignal("addr", Pins("AE23 AE22 AG18 AG12 AG15 AG23 AF19 AE12 AG16 AF13 AG20 AF23", + "AH17 AH15 L20 J22 H22 L15 L16 K22 K21 K16 J15")), + Subsignal("addr_gp", Pins("L21 G22 K23 K14 L14 J12")), + Subsignal("data", Pins("AF15 AE16 AE21 AD20 AF16 AE17 AE19 AD19 AG22 AH22 AH12 AG13", + "AH20 AH19 AH14 AH13")), + Subsignal("rdy", Pins("K12")), + IOStandard("LVCMOS33") + ), + ("roach_clocks", 0, + Subsignal("epb_clk", Pins("AH18"), IOStandard("LVCMOS33")), + Subsignal("sys_clk_n", Pins("H13")), + Subsignal("sys_clk_p", Pins("J14")), + Subsignal("aux0_clk_p", Pins("G15")), + Subsignal("aux0_clk_n", Pins("G16")), + Subsignal("aux1_clk_p", Pins("H14")), + Subsignal("aux1_clk_n", Pins("H15")), + Subsignal("dly_clk_n", Pins("J17")), + Subsignal("dly_clk_p", Pins("J16")), + ), +] + + +class Platform(XilinxPlatform): + def __init__(self): + XilinxPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io) diff --git a/migen/build/platforms/sim.py b/migen/build/platforms/sim.py new file mode 100644 index 00000000..0e4a40d1 --- /dev/null +++ b/migen/build/platforms/sim.py @@ -0,0 +1,45 @@ +from migen.build.generic_platform import * +from migen.build.sim import SimPlatform + + +class SimPins(Pins): + def __init__(self, n): + Pins.__init__(self, "s "*n) + +_io = [ + ("sys_clk", 0, SimPins(1)), + ("sys_rst", 0, SimPins(1)), + ("serial", 0, + Subsignal("source_stb", SimPins(1)), + Subsignal("source_ack", SimPins(1)), + Subsignal("source_data", SimPins(8)), + + Subsignal("sink_stb", SimPins(1)), + Subsignal("sink_ack", SimPins(1)), + Subsignal("sink_data", SimPins(8)), + ), + ("eth_clocks", 0, + Subsignal("none", SimPins(1)), + ), + ("eth", 0, + Subsignal("source_stb", SimPins(1)), + Subsignal("source_ack", SimPins(1)), + Subsignal("source_data", SimPins(8)), + + Subsignal("sink_stb", SimPins(1)), + Subsignal("sink_ack", SimPins(1)), + Subsignal("sink_data", SimPins(8)), + ), +] + + +class Platform(SimPlatform): + is_sim = True + default_clk_name = "sys_clk" + default_clk_period = 1000 # on modern computers simulate at ~ 1MHz + + def __init__(self): + SimPlatform.__init__(self, "SIM", _io) + + def do_finalize(self, fragment): + pass diff --git a/migen/build/platforms/usrp_b100.py b/migen/build/platforms/usrp_b100.py new file mode 100644 index 00000000..2e162738 --- /dev/null +++ b/migen/build/platforms/usrp_b100.py @@ -0,0 +1,152 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_io = [ + ("clk64", 0, + Subsignal("p", Pins("R7")), + Subsignal("n", Pins("T7")), + IOStandard("LVDS_33"), + Misc("DIFF_TERM=TRUE"), + ), + + ("pps", 0, Pins("M14"), Misc("TIG")), + ("reset_n", 0, Pins("D5"), Misc("TIG")), + ("codec_reset", 0, Pins("B14")), + # recycles fpga_cfg_cclk for reset from fw + ("ext_reset", 0, Pins("R14")), + + ("i2c", 0, + Subsignal("sda", Pins("T13")), + Subsignal("scl", Pins("R13")), + ), + + ("cgen", 0, + Subsignal("st_ld", Pins("M13")), + Subsignal("st_refmon", Pins("J14")), + Subsignal("st_status", Pins("P6")), + Subsignal("ref_sel", Pins("T2")), + Subsignal("sync_b", Pins("H15")), + ), + + ("fx2_ifclk", 0, Pins("T8")), + ("fx2_gpif", 0, + Subsignal("d", Pins("P8 P9 N9 T9 R9 P11 P13 N12 " + "T3 R3 P5 N6 T6 T5 N8 P7")), + Subsignal("ctl", Pins("M7 M9 M11 P12")), + Subsignal("slwr", Pins("T4")), # rdy0 + Subsignal("slrd", Pins("R5")), # rdy1 + # Subsignal("rdy2", Pins("T10")), + # Subsignal("rdy3", Pins("N11")), + # Subsignal("cs", Pins("P12")), + Subsignal("sloe", Pins("R11")), + Subsignal("pktend", Pins("P10")), + Subsignal("adr", Pins("T11 H16")), + ), + + ("user_led", 0, Pins("P4"), Misc("TIG")), + ("user_led", 1, Pins("N4"), Misc("TIG")), + ("user_led", 2, Pins("R2"), Misc("TIG")), + + ("debug_clk", 0, Pins("K15 K14")), + ("debug", 0, Pins( + "K16 J16 C16 C15 E13 D14 D16 D15 " + "E14 F13 G13 F14 E16 F15 H13 G14 " + "G16 F16 J12 J13 L14 L16 M15 M16 " + "L13 K13 P16 N16 R15 P15 N13 N14")), + + ("adc", 0, + Subsignal("sync", Pins("D10")), + Subsignal("d", Pins("A4 B3 A3 D9 C10 A9 C9 D8 " + "C8 B8 A8 B15")), + ), + ("dac", 0, + Subsignal("blank", Pins("K1")), + Subsignal("sync", Pins("J2")), + Subsignal("d", Pins("J1 H3 J3 G2 H1 N3 M4 R1 " + "P2 P1 M1 N1 M3 L4")), + ), + ("codec_spi", 0, + Subsignal("sclk", Pins("K3")), + Subsignal("sen", Pins("D13")), + Subsignal("mosi", Pins("C13")), + Subsignal("miso", Pins("G4")), + ), + + ("aux_spi", 0, + Subsignal("sen", Pins("C12")), + Subsignal("sclk", Pins("D12")), + Subsignal("miso", Pins("J5")), + ), + ("rx_io", 0, Pins("D7 C6 A6 B6 E9 A7 C7 B10 " + "A10 C11 A11 D11 B12 A12 A14 A13")), + ("tx_io", 0, Pins("K4 L3 L2 F1 F3 G3 E3 E2 " + "E4 F4 D1 E1 D4 D3 C2 C1")), + ("rx_spi", 0, + Subsignal("miso", Pins("E6")), + Subsignal("sen", Pins("B4")), + Subsignal("mosi", Pins("A5")), + Subsignal("sclk", Pins("C5")), + ), + ("tx_spi", 0, + Subsignal("miso", Pins("J4")), + Subsignal("sen", Pins("N2")), + Subsignal("mosi", Pins("L1")), + Subsignal("sclk", Pins("G1")), + ), + + # these are just for information. do not request. + ("mystery_bus", 0, Pins("C4 E7")), + ("fpga_cfg", + Subsignal("din", Pins("T14")), + Subsignal("cclk", Pins("R14")), + Subsignal("init_b", Pins("T12")), + Subsignal("prog_b", Pins("A2")), + Subsignal("done", Pins("T15")), + ), + ("jtag", + Subsignal("tms", Pins("B2")), + Subsignal("tdo", Pins("B16")), + Subsignal("tdi", Pins("B1")), + Subsignal("tck", Pins("A15")), + ), +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk64" + default_clk_period = 15.625 + + def __init__(self): + XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io) + self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp" + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + + self.add_platform_command(""" +TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; +""") + + try: + ifclk = self.lookup_request("fx2_ifclk") + gpif = self.lookup_request("fx2_gpif") + for i, d in [(gpif.d, "in"), (gpif.d, "out"), + (gpif.ctl, "in"), (gpif.adr, "out"), + (gpif.slwr, "out"), (gpif.sloe, "out"), + (gpif.slrd, "out"), (gpif.pktend, "out")]: + if flen(i) > 1: + q = "(*)" + else: + q = "" + self.add_platform_command(""" +INST "{i}%s" TNM = gpif_net_%s; +""" % (q, d), i=i) + self.add_platform_command(""" +NET "{ifclk}" TNM_NET = "GRPifclk"; +TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%; +TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING; +TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING; +""", ifclk=ifclk) + except ConstraintError: + pass diff --git a/migen/build/platforms/versa.py b/migen/build/platforms/versa.py new file mode 100644 index 00000000..dc8dd53d --- /dev/null +++ b/migen/build/platforms/versa.py @@ -0,0 +1,96 @@ +# This file is Copyright (c) 2013 Florent Kermarrec +# License: BSD + +from migen.build.generic_platform import * +from migen.build.lattice import LatticePlatform +from migen.build.lattice.programmer import LatticeProgrammer + + +_io = [ + ("clk100", 0, Pins("L5"), IOStandard("LVDS25")), + ("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")), + + ("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")), + ("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")), + ("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")), + ("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")), + ("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")), + ("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")), + + ("user_dip_btn", 0, Pins("J7"), IOStandard("LVCMOS15")), + ("user_dip_btn", 1, Pins("J6"), IOStandard("LVCMOS15")), + ("user_dip_btn", 2, Pins("H2"), IOStandard("LVCMOS15")), + ("user_dip_btn", 3, Pins("H3"), IOStandard("LVCMOS15")), + ("user_dip_btn", 4, Pins("J3"), IOStandard("LVCMOS15")), + ("user_dip_btn", 5, Pins("K3"), IOStandard("LVCMOS15")), + ("user_dip_btn", 6, Pins("J2"), IOStandard("LVCMOS15")), + ("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")), + + ("serial", 0, + Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")), # X4 IO0 + Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")), # X4 IO1 + ), + + ("eth_clocks", 0, + Subsignal("tx", Pins("C12")), + Subsignal("gtx", Pins("M2")), + Subsignal("rx", Pins("L4")), + IOStandard("LVCMOS33") + ), + ("eth", 0, + Subsignal("rst_n", Pins("L3")), + Subsignal("mdio", Pins("L2")), + Subsignal("mdc", Pins("V4")), + Subsignal("dv", Pins("M1")), + Subsignal("rx_er", Pins("M4")), + Subsignal("rx_data", Pins("M5 N1 N6 P6 T2 R2 P5 P3")), + Subsignal("tx_en", Pins("V3")), + Subsignal("tx_data", Pins("V1 U1 R3 P1 N5 N3 N4 N2")), + Subsignal("col", Pins("R1")), + Subsignal("crs", Pins("P4")), + IOStandard("LVCMOS33") + ), + + ("eth_clocks", 1, + Subsignal("tx", Pins("M21")), + Subsignal("gtx", Pins("M19")), + Subsignal("rx", Pins("N19")), + IOStandard("LVCMOS33") + ), + ("eth", 1, + Subsignal("rst_n", Pins("R21")), + Subsignal("mdio", Pins("U16")), + Subsignal("mdc", Pins("Y18")), + Subsignal("dv", Pins("U15")), + Subsignal("rx_er", Pins("V20")), + Subsignal("rx_data", Pins("AB17 AA17 R19 V21 T17 R18 W21 Y21")), + Subsignal("tx_en", Pins("V22")), + Subsignal("tx_data", Pins("W22 R16 P17 Y22 T21 U22 P20 U20")), + Subsignal("col", Pins("N18")), + Subsignal("crs", Pins("P19")), + IOStandard("LVCMOS33") + ), +] + + +class Platform(LatticePlatform): + default_clk_name = "clk100" + default_clk_period = 10 + + def __init__(self): + LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io) + + def do_finalize(self, fragment): + LatticePlatform.do_finalize(self, fragment) + try: + self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) + except ConstraintError: + pass + try: + self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0) + except ConstraintError: + pass + def create_programmer(self): + return LatticeProgrammer() diff --git a/migen/build/platforms/zedboard.py b/migen/build/platforms/zedboard.py new file mode 100644 index 00000000..b5d3dcc2 --- /dev/null +++ b/migen/build/platforms/zedboard.py @@ -0,0 +1,145 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +# Bank 34 and 35 voltage depend on J18 jumper setting +_io = [ + ("clk100", 0, Pins("Y9"), IOStandard("LVCMOS33")), + + ("user_btn", 0, Pins("P16"), IOStandard("LVCMOS18")), # center + ("user_btn", 1, Pins("R16"), IOStandard("LVCMOS18")), # down + ("user_btn", 2, Pins("N15"), IOStandard("LVCMOS18")), # left + ("user_btn", 3, Pins("R18"), IOStandard("LVCMOS18")), # right + ("user_btn", 4, Pins("T18"), IOStandard("LVCMOS18")), # up + + ("user_sw", 0, Pins("F22"), IOStandard("LVCMOS18")), + ("user_sw", 1, Pins("G22"), IOStandard("LVCMOS18")), + ("user_sw", 2, Pins("H22"), IOStandard("LVCMOS18")), + ("user_sw", 3, Pins("F21"), IOStandard("LVCMOS18")), + ("user_sw", 4, Pins("H19"), IOStandard("LVCMOS18")), + ("user_sw", 5, Pins("H18"), IOStandard("LVCMOS18")), + ("user_sw", 6, Pins("H17"), IOStandard("LVCMOS18")), + ("user_sw", 7, Pins("M15"), IOStandard("LVCMOS18")), + + ("user_led", 0, Pins("T22"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("T21"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("U22"), IOStandard("LVCMOS33")), + ("user_led", 3, Pins("U21"), IOStandard("LVCMOS33")), + ("user_led", 4, Pins("V22"), IOStandard("LVCMOS33")), + ("user_led", 5, Pins("W22"), IOStandard("LVCMOS33")), + ("user_led", 6, Pins("U19"), IOStandard("LVCMOS33")), + ("user_led", 7, Pins("U14"), IOStandard("LVCMOS33")), + + # A + ("pmod", 0, Pins("Y11 AA11 Y10 AA9 AB11 AB10 AB9 AA8"), + IOStandard("LVCMOS33")), + # B + ("pmod", 1, Pins("W12 W11 V10 W8 V12 W10 V9 V8"), + IOStandard("LVCMOS33")), + # C + ("pmod", 2, + Subsignal("n", Pins("AB6 AA4 T6 U4")), + Subsignal("p", Pins("AB7 Y4 R6 T4")), + IOStandard("LVCMOS33")), + # D + ("pmod", 3, + Subsignal("n", Pins("W7 V4 W5 U5")), + Subsignal("p", Pins("V7 V5 W6 U6")), + IOStandard("LVCMOS33")), + + ("audio", 0, + Subsignal("adr", Pins("AB1 Y5")), + Subsignal("gpio", Pins("Y8 AA7 AA6 Y6")), + Subsignal("mclk", Pins("AB2")), + Subsignal("sck", Pins("AB4")), + Subsignal("sda", Pins("AB5")), + IOStandard("LVCMOS33")), + + ("oled", 0, + Subsignal("dc", Pins("U10")), + Subsignal("res", Pins("U9")), + Subsignal("sclk", Pins("AB12")), + Subsignal("sdin", Pins("AA12")), + Subsignal("vbat", Pins("U11")), + Subsignal("vdd", Pins("U12")), + IOStandard("LVCMOS33")), + + ("hdmi", 0, + Subsignal("clk", Pins("W18")), + Subsignal("d", Pins( + "Y13 AA13 AA14 Y14 AB15 AB16 AA16 AB17 " + "AA17 Y15 W13 W15 V15 U17 V14 V13")), + Subsignal("de", Pins("U16")), + Subsignal("hsync", Pins("V17")), + Subsignal("vsync", Pins("W17")), + Subsignal("int", Pins("W16")), + Subsignal("scl", Pins("AA18")), + Subsignal("sda", Pins("Y16")), + Subsignal("spdif", Pins("U15")), + Subsignal("spdifo", Pins("Y18")), + IOStandard("LVCMOS33")), + + ("netic16", 0, + Subsignal("w20", Pins("W20")), + Subsignal("w21", Pins("W21")), + IOStandard("LVCMOS33")), + + ("vga", 0, + Subsignal("r", Pins("V20 U20 V19 V18")), + Subsignal("g", Pins("AB22 AA22 AB21 AA21")), + Subsignal("b", Pins("Y21 Y20 AB20 AB19")), + Subsignal("hsync_n", Pins("AA19")), + Subsignal("vsync_n", Pins("Y19")), + IOStandard("LVCMOS33")), + + ("usb_otg", 0, + Subsignal("vbusoc", Pins("L16")), + Subsignal("reset_n", Pins("G17")), + IOStandard("LVCMOS18")), + + ("pudc_b", 0, Pins("K16"), IOStandard("LVCMOS18")), + + ("xadc", 0, + Subsignal("gio", Pins("H15 R15 K15 J15")), + Subsignal("ad0_n", Pins("E16")), + Subsignal("ad0_p", Pins("F16")), + Subsignal("ad8_n", Pins("D17")), + Subsignal("ad8_p", Pins("D16")), + IOStandard("LVCMOS18")), + + ("fmc_clocks", 0, + Subsignal("clk0_n", Pins("L19")), + Subsignal("clk0_p", Pins("L18")), + Subsignal("clk1_n", Pins("C19")), + Subsignal("clk1_p", Pins("D18")), + IOStandard("LVCMOS18")), + + ("fmc", 0, + Subsignal("scl", Pins("R7")), + Subsignal("sda", Pins("U7")), + + Subsignal("prsnt", Pins("AB14")), + + # 0, 1, 17, 18 can be clock signals + Subsignal("la_n", Pins( + "M20 N20 P18 P22 M22 K18 L22 T17 " + "J22 R21 T19 N18 P21 M17 K20 J17 " + "K21 B20 C20 G16 G21 E20 F19 D15 " + "A19 C22 E18 D21 A17 C18 B15 B17 " + "A22 B22")), + Subsignal("la_p", Pins( + "M19 N19 P17 N22 M21 J18 L21 T16 " + "J21 R20 R19 N17 P20 L17 K19 J16 " + "J20 B19 D20 G15 G20 E19 G19 E15 " + "A18 D22 F18 E21 A16 C17 C15 B16 " + "A21 B21")), + IOStandard("LVCMOS18")), +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 10 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io) diff --git a/migen/build/platforms/ztex_115d.py b/migen/build/platforms/ztex_115d.py new file mode 100644 index 00000000..253a121c --- /dev/null +++ b/migen/build/platforms/ztex_115d.py @@ -0,0 +1,110 @@ +from migen.build.generic_platform import * +from migen.build.xilinx import XilinxPlatform + + +_io = [ + ("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")), + ("clk_if", 0, Pins("K20"), IOStandard("LVCMOS33")), + ("rst", 0, Pins("A18")), + # PROG_B and DONE: AA1 U16 + + ("fx2", 0, + Subsignal("sloe", Pins("U15"), Drive(12)), # M1 + Subsignal("slrd", Pins("N22"), Drive(12)), + Subsignal("slwr", Pins("M22"), Drive(12)), + Subsignal("pktend", Pins("AB5"), Drive(12)), # CSO + Subsignal("fifoadr", Pins("W17 Y18"), Drive(12)), # CCLK M0 + Subsignal("cont", Pins("G20")), + Subsignal("fd", Pins("Y17 V13 W13 AA8 AB8 W6 Y6 Y9 " + "V21 V22 U20 U22 R20 R22 P18 P19")), + Subsignal("flag", Pins("F20 F19 F18 AB17")), # - - - CSI/MOSI + Subsignal("rdy25", Pins("M21 K21 K22 J21")), + Subsignal("ctl35", Pins("D19 E20 N20")), + Subsignal("int45", Pins("C18 V17")), + Subsignal("pc", Pins("G20 T10 V5 AB9 G19 H20 H19 H18")), + # - DOUT/BUSY INIT_B RDWR_B DO CS CLK DI + IOStandard("LVCMOS33")), + + ("mm", 0, + Subsignal("a", Pins("M20 M19 M18 N19 T19 T21 T22 R19 ", + "P20 P21 P22 J22 H21 H22 G22 F21")), + Subsignal("d", Pins("D20 C20 C19 B21 B20 J19 K19 L19"), Drive(2)), + Subsignal("wr_n", Pins("C22")), + Subsignal("rd_n", Pins("D21")), + Subsignal("psen_n", Pins("D22")), + IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("B22"), Misc("SLEW=QUIETIO")), + Subsignal("rx", Pins("A21"), Misc("PULLDOWN")), + IOStandard("LVCMOS33")), + + ("ddram_clock", 0, + Subsignal("p", Pins("F2"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("n", Pins("F1"), Misc("OUT_TERM=UNTUNED_50")), + IOStandard("SSTL18_II")), + + ("ddram", 0, + Subsignal("dqs", Pins("L3 T2"), IOStandard("SSTL18_II"), # DIFF_ + Misc("IN_TERM=NONE")), + Subsignal("dqs_n", Pins("L1 T1"), IOStandard("SSTL18_II"), # DIFF_ + Misc("IN_TERM=NONE")), + Subsignal("dm", Pins("H1 H2"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("dq", Pins("M1 M2 J1 K2 J3 K1 N3 N1 " + "U1 U3 P1 R3 P2 R1 V2 V1"), Misc("IN_TERM=NONE")), + Subsignal("ras_n", Pins("N4"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("cas_n", Pins("P3"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("a", Pins("M5 K6 B1 J4 L4 K3 M4 K5 G3 G1 K4 C3 C1"), + Misc("OUT_TERM=UNTUNED_50")), + Subsignal("ba", Pins("E3 E1 D1"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("cke", Pins("J6"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("cs_n", Pins("H6")), # NC! + Subsignal("odt", Pins("M3"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("we_n", Pins("D2")), + Subsignal("rzq", Pins("AA2")), + Subsignal("zio", Pins("Y2")), + IOStandard("SSTL18_II")), + + ("i2c", 0, + Subsignal("scl", Pins("F22")), + Subsignal("sda", Pins("E22")), + IOStandard("LVCMOS33")), + + ("sd", 0, + Subsignal("sck", Pins("H11")), + Subsignal("d3", Pins("H14")), + Subsignal("d", Pins("P10")), + Subsignal("d1", Pins("T18")), + Subsignal("d2", Pins("R17")), + Subsignal("cmd", Pins("H13")), + IOStandard("LVCMOS33")), + +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk_if" + default_clk_period = 20 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io) + self.add_platform_command(""" +CONFIG VCCAUX = "2.5"; +""") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + + try: + clk_if = self.lookup_request("clk_if") + clk_fx = self.lookup_request("clk_fx") + self.add_platform_command(""" +NET "{clk_if}" TNM_NET = "GRPclk_if"; +NET "{clk_fx}" TNM_NET = "GRPclk_fx"; +TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%; +TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%; +TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY; +TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY; +""", clk_if=clk_if, clk_fx=clk_fx) + except ConstraintError: + pass diff --git a/migen/build/sim/__init__.py b/migen/build/sim/__init__.py new file mode 100644 index 00000000..adbba1c4 --- /dev/null +++ b/migen/build/sim/__init__.py @@ -0,0 +1 @@ +from migen.build.sim.platform import SimPlatform diff --git a/migen/build/sim/common.py b/migen/build/sim/common.py new file mode 100644 index 00000000..38741fd4 --- /dev/null +++ b/migen/build/sim/common.py @@ -0,0 +1 @@ +sim_special_overrides = {} diff --git a/migen/build/sim/dut_tb.cpp b/migen/build/sim/dut_tb.cpp new file mode 100644 index 00000000..0e8dac7e --- /dev/null +++ b/migen/build/sim/dut_tb.cpp @@ -0,0 +1,399 @@ +// This file is Copyright (c) 2015 Florent Kermarrec +// License: BSD +#include "Vdut.h" +#include "verilated.h" +#include "verilated_vcd_c.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* ios */ + +#ifdef SERIAL_SOURCE_STB +#define WITH_SERIAL +#endif + +#ifdef ETH_SOURCE_STB +#define WITH_ETH +#endif + +#define MAX(a,b) (((a)>(b))?(a):(b)) +#define MIN(a,b) (((a)<(b))?(a):(b)) + +int trace = 0; + +vluint64_t main_time = 0; +double sc_time_stamp() +{ + return main_time; +} + +/* Sim struct */ +struct sim { + bool run; + + unsigned int tick; + clock_t start; + clock_t end; + float speed; + +#ifdef WITH_SERIAL_PTY + char serial_dev[64]; + int serial_fd; + unsigned char serial_rx_data; + unsigned char serial_tx_data; +#endif +#ifdef WITH_ETH + const char *eth_dev; + const char *eth_tap; + int eth_fd; + unsigned char eth_txbuffer[2048]; + unsigned char eth_rxbuffer[2048]; + int eth_txbuffer_len; + int eth_rxbuffer_len; + int eth_rxbuffer_pos; + int eth_last_source_stb; +#endif +}; + +/* Serial functions */ +#ifndef WITH_SERIAL_PTY +struct termios orig_termios; + +void reset_terminal_mode(void) +{ + tcsetattr(0, TCSANOW, &orig_termios); +} + +void set_conio_terminal_mode(void) +{ + struct termios new_termios; + + /* take two copies - one for now, one for later */ + tcgetattr(0, &orig_termios); + memcpy(&new_termios, &orig_termios, sizeof(new_termios)); + + /* register cleanup handler, and set the new terminal mode */ + atexit(reset_terminal_mode); + cfmakeraw(&new_termios); + tcsetattr(0, TCSANOW, &new_termios); +} + +int kbhit(void) +{ + struct timeval tv = { 0L, 0L }; + fd_set fds; + FD_ZERO(&fds); + FD_SET(0, &fds); + return select(1, &fds, NULL, NULL, &tv); +} + +int getch(void) +{ + int r; + unsigned char c; + if((r = read(0, &c, sizeof(c))) < 0) { + return r; + } else { + return c; + } +} +#endif + +/* Ethernet functions */ +/* create tap: + openvpn --mktun --dev tap0 + ifconfig tap0 192.168.0.14 up + mknod /dev/net/tap0 c 10 200 + delete tap: + openvpn --rmtun --dev tap0 */ +#ifdef WITH_ETH +void eth_init(struct sim *s, const char *dev, const char*tap) +{ + s->eth_txbuffer_len = 0; + s->eth_rxbuffer_len = 0; + s->eth_rxbuffer_pos = 0; + s->eth_last_source_stb = 0; + s->eth_dev = dev; + s->eth_tap = tap; +} + +void eth_open(struct sim *s) +{ + + struct ifreq ifr; + s->eth_fd = open (s->eth_dev, O_RDWR); + if(s->eth_fd < 0) { + fprintf(stderr, " Could not open dev %s\n", s->eth_dev); + return; + } + + memset(&ifr, 0, sizeof(ifr)); + ifr.ifr_flags = IFF_TAP | IFF_NO_PI; + strncpy(ifr.ifr_name, s->eth_tap, IFNAMSIZ); + + if(ioctl(s->eth_fd, TUNSETIFF, (void *) &ifr) < 0) { + fprintf(stderr, " Could not set %s\n", s->eth_tap); + close(s->eth_fd); + } + return; +} + +int eth_close(struct sim *s) +{ + if(s->eth_fd < 0) + close(s->eth_fd); +} + +void eth_write(struct sim *s, unsigned char *buf, int len) +{ + write(s->eth_fd, buf, len); +} + +int eth_read(struct sim *s, unsigned char *buf) +{ + + struct pollfd fds[1]; + int n; + int len; + + fds[0].fd = s->eth_fd; + fds[0].events = POLLIN; + + n = poll(fds, 1, 0); + if((n > 0) && ((fds[0].revents & POLLIN) == POLLIN)) { + len = read(s->eth_fd, buf, 1532); + } else { + len = 0; + } + return len; +} +#endif + +Vdut* dut; +VerilatedVcdC* tfp; + +#ifndef WITH_SERIAL_PTY +int console_service(struct sim *s) +{ + /* fpga --> console */ + SERIAL_SOURCE_ACK = 1; + if(SERIAL_SOURCE_STB == 1) { + if(SERIAL_SOURCE_DATA == '\n') + putchar('\r'); + putchar(SERIAL_SOURCE_DATA); + fflush(stdout); + } + + /* console --> fpga */ + SERIAL_SINK_STB = 0; + if(s->tick%(1000) == 0) { + if(kbhit()) { + char c = getch(); + if(c == 27 && !kbhit()) { + printf("\r\n"); + return -1; + } else { + SERIAL_SINK_STB = 1; + SERIAL_SINK_DATA = c; + } + } + } + return 0; +} +#else +void console_init(struct sim *s) +{ + FILE *f; + f = fopen("/tmp/simserial","r"); + fscanf(f, "%[^\n]", s->serial_dev); + fclose(f); + return; +} + +void console_open(struct sim *s) +{ + s->serial_fd = open(s->serial_dev, O_RDWR); + if(s->serial_fd < 0) { + fprintf(stderr, " Could not open dev %s\n", s->serial_dev); + return; + } + return; +} + +int console_close(struct sim *s) +{ + if(s->serial_fd < 0) + close(s->serial_fd); +} + +void console_write(struct sim *s, unsigned char *buf, int len) +{ + write(s->serial_fd, buf, len); +} + +int console_read(struct sim *s, unsigned char *buf) +{ + struct pollfd fds[1]; + int n; + int len; + + fds[0].fd = s->serial_fd; + fds[0].events = POLLIN; + + n = poll(fds, 1, 0); + if((n > 0) && ((fds[0].revents & POLLIN) == POLLIN)) { + len = read(s->serial_fd, buf, 1); + } else { + len = 0; + } + return len; +} + +int console_service(struct sim *s) +{ + /* fpga --> console */ + SERIAL_SOURCE_ACK = 1; + if(SERIAL_SOURCE_STB == 1) { + s->serial_tx_data = SERIAL_SOURCE_DATA; + console_write(s, &(s->serial_tx_data), 1); + } + + /* console --> fpga */ + SERIAL_SINK_STB = 0; + if(console_read(s, &(s->serial_rx_data))) + { + SERIAL_SINK_STB = 1; + SERIAL_SINK_DATA = s->serial_rx_data; + } + return 0; +} +#endif + +#ifdef WITH_ETH +int ethernet_service(struct sim *s) { + /* fpga --> tap */ + ETH_SOURCE_ACK = 1; + if(ETH_SOURCE_STB == 1) { + s->eth_txbuffer[s->eth_txbuffer_len] = ETH_SOURCE_DATA; + s->eth_txbuffer_len++; + } else { + if(s->eth_last_source_stb) { + eth_write(s, s->eth_txbuffer, s->eth_txbuffer_len); + s->eth_txbuffer_len = 0; + } + } + s->eth_last_source_stb = ETH_SOURCE_STB; + + /* tap --> fpga */ + if(s->eth_rxbuffer_len == 0) { + ETH_SINK_STB = 0; + s->eth_rxbuffer_pos = 0; + s->eth_rxbuffer_len = eth_read(s, s->eth_rxbuffer); + } else { + if(s->eth_rxbuffer_pos < MAX(s->eth_rxbuffer_len, 60)) { + ETH_SINK_STB = 1; + ETH_SINK_DATA = s->eth_rxbuffer[s->eth_rxbuffer_pos]; + s->eth_rxbuffer_pos++; + } else { + ETH_SINK_STB = 0; + s->eth_rxbuffer_len = 0; + memset(s->eth_rxbuffer, 0, 1532); + } + } +} +#endif + +void sim_tick(struct sim *s) +{ + SYS_CLK = s->tick%2; + dut->eval(); + if(trace) + tfp->dump(s->tick); + s->tick++; +} + +void sim_init(struct sim *s) +{ + int i; + s->tick = 0; +#ifdef SYS_RST + SYS_RST = 1; + SYS_CLK = 0; + for (i=0; i<8; i++) + sim_tick(s); + SYS_RST = 0; +#endif + s->start = clock(); +} + +int main(int argc, char **argv, char **env) +{ + float speed; + +#ifndef WITH_SERIAL_PTY + set_conio_terminal_mode(); +#endif + + Verilated::commandArgs(argc, argv); + dut = new Vdut; + + Verilated::traceEverOn(true); + tfp = new VerilatedVcdC; + dut->trace(tfp, 99); + tfp->open("dut.vcd"); + + struct sim s; + sim_init(&s); + +#ifdef WITH_SERIAL_PTY + console_init(&s); + console_open(&s); +#endif + +#ifdef WITH_ETH + eth_init(&s, "/dev/net/tap0", "tap0"); // XXX get this from /tmp/simethernet + eth_open(&s); +#endif + + s.run = true; + while(s.run) { + sim_tick(&s); + if(SYS_CLK) { +#ifdef WITH_SERIAL + if(console_service(&s) != 0) + s.run = false; +#endif +#ifdef WITH_ETH + ethernet_service(&s); +#endif + } + } + s.end = clock(); + + speed = (s.tick/2)/((s.end-s.start)/CLOCKS_PER_SEC); + + printf("average speed: %3.3f MHz\n\r", speed/1000000); + + tfp->close(); + + +#ifdef WITH_SERIAL_PTY + console_close(&s); +#endif +#ifdef WITH_ETH + eth_close(&s); +#endif + + exit(0); +} diff --git a/migen/build/sim/platform.py b/migen/build/sim/platform.py new file mode 100644 index 00000000..0c5e17d2 --- /dev/null +++ b/migen/build/sim/platform.py @@ -0,0 +1,20 @@ +from migen.build.generic_platform import GenericPlatform +from migen.build.sim import common, verilator + + +class SimPlatform(GenericPlatform): + def __init__(self, *args, toolchain="verilator", **kwargs): + GenericPlatform.__init__(self, *args, **kwargs) + if toolchain == "verilator": + self.toolchain = verilator.SimVerilatorToolchain() + else: + raise ValueError("Unknown toolchain") + + def get_verilog(self, *args, special_overrides=dict(), **kwargs): + so = dict(common.sim_special_overrides) + so.update(special_overrides) + return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) + + def build(self, *args, **kwargs): + return self.toolchain.build(self, *args, **kwargs) + diff --git a/migen/build/sim/verilator.py b/migen/build/sim/verilator.py new file mode 100644 index 00000000..fd1d8be9 --- /dev/null +++ b/migen/build/sim/verilator.py @@ -0,0 +1,152 @@ +# This file is Copyright (c) 2015 Florent Kermarrec +# License: BSD + +import os +import subprocess + +from migen.fhdl.std import * +from migen.fhdl.structure import _Fragment + +from migen.build import tools +from migen.build.generic_platform import * +from migen.build.sim import common + + +def _build_tb(platform, vns, serial, template): + + def io_name(ressource, subsignal=None): + res = platform.lookup_request(ressource) + if subsignal is not None: + res = getattr(res, subsignal) + return vns.get_name(res) + + ios = """ +#define SYS_CLK dut->{sys_clk} +""".format(sys_clk=io_name("sys_clk")) + + if serial == "pty": + ios += "#define WITH_SERIAL_PTY" + elif serial == "console": + pass + else: + raise ValueError + try: + ios += """ +#define SERIAL_SOURCE_STB dut->{serial_source_stb} +#define SERIAL_SOURCE_ACK dut->{serial_source_ack} +#define SERIAL_SOURCE_DATA dut->{serial_source_data} + +#define SERIAL_SINK_STB dut->{serial_sink_stb} +#define SERIAL_SINK_ACK dut->{serial_sink_ack} +#define SERIAL_SINK_DATA dut->{serial_sink_data} +""".format( + serial_source_stb=io_name("serial", "source_stb"), + serial_source_ack=io_name("serial", "source_ack"), + serial_source_data=io_name("serial", "source_data"), + + serial_sink_stb=io_name("serial", "sink_stb"), + serial_sink_ack=io_name("serial", "sink_ack"), + serial_sink_data=io_name("serial", "sink_data"), + ) + except: + pass + + try: + ios += """ +#define ETH_SOURCE_STB dut->{eth_source_stb} +#define ETH_SOURCE_ACK dut->{eth_source_ack} +#define ETH_SOURCE_DATA dut->{eth_source_data} + +#define ETH_SINK_STB dut->{eth_sink_stb} +#define ETH_SINK_ACK dut->{eth_sink_ack} +#define ETH_SINK_DATA dut->{eth_sink_data} +""".format( + eth_source_stb=io_name("eth", "source_stb"), + eth_source_ack=io_name("eth", "source_ack"), + eth_source_data=io_name("eth", "source_data"), + + eth_sink_stb=io_name("eth", "sink_stb"), + eth_sink_ack=io_name("eth", "sink_ack"), + eth_sink_data=io_name("eth", "sink_data"), + ) + except: + pass + + content = "" + f = open(template, "r") + done = False + for l in f: + content += l + if "/* ios */" in l and not done: + content += ios + done = True + + f.close() + tools.write_to_file("dut_tb.cpp", content) + + +def _build_sim(platform, vns, build_name, include_paths, sim_path, serial, verbose): + include = "" + for path in include_paths: + include += "-I"+path+" " + + build_script_contents = """# Autogenerated by Migen + rm -rf obj_dir/ +verilator {disable_warnings} -O3 --cc dut.v --exe dut_tb.cpp -LDFLAGS "-lpthread" -trace {include} +make -j -C obj_dir/ -f Vdut.mk Vdut + +""".format( + disable_warnings="-Wno-fatal", + include=include) + build_script_file = "build_" + build_name + ".sh" + tools.write_to_file(build_script_file, build_script_contents, force_unix=True) + + _build_tb(platform, vns, serial, os.path.join("..", sim_path, "dut_tb.cpp")) + if verbose: + r = subprocess.call(["bash", build_script_file]) + else: + r = subprocess.call(["bash", build_script_file], stdout=subprocess.DEVNULL, stderr=subprocess.STDOUT) + if r != 0: + raise OSError("Subprocess failed") + + +def _run_sim(build_name): + run_script_contents = """obj_dir/Vdut +""" + run_script_file = "run_" + build_name + ".sh" + tools.write_to_file(run_script_file, run_script_contents, force_unix=True) + r = subprocess.call(["bash", run_script_file]) + if r != 0: + raise OSError("Subprocess failed") + + +class SimVerilatorToolchain: + # XXX fir sim_path + def build(self, platform, fragment, build_dir="build", build_name="top", + sim_path="../migen/migen/build/sim/", serial="console", + run=True, verbose=False): + tools.mkdir_noerror(build_dir) + os.chdir(build_dir) + + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + platform.finalize(fragment) + + v_output = platform.get_verilog(fragment) + named_sc, named_pc = platform.resolve_signals(v_output.ns) + v_output.write("dut.v") + + include_paths = [] + for source in platform.sources: + path = os.path.dirname(source[0]).replace("\\", "\/") + if path not in include_paths: + include_paths.append(path) + include_paths += platform.verilog_include_paths + _build_sim(platform, v_output.ns, build_name, include_paths, sim_path, serial, verbose) + + if run: + _run_sim(build_name) + + os.chdir("..") + + return v_output.ns diff --git a/migen/build/tools.py b/migen/build/tools.py new file mode 100644 index 00000000..9e0880d5 --- /dev/null +++ b/migen/build/tools.py @@ -0,0 +1,42 @@ +import os +import struct +from distutils.version import StrictVersion + + +def mkdir_noerror(d): + try: + os.mkdir(d) + except OSError: + pass + + +def language_by_filename(name): + extension = name.rsplit(".")[-1] + if extension in ["v", "vh", "vo"]: + return "verilog" + if extension in ["vhd", "vhdl", "vho"]: + return "vhdl" + return None + + +def write_to_file(filename, contents, force_unix=False): + newline = None + if force_unix: + newline = "\n" + with open(filename, "w", newline=newline) as f: + f.write(contents) + + +def arch_bits(): + return struct.calcsize("P")*8 + + +def versions(path): + for n in os.listdir(path): + full = os.path.join(path, n) + if not os.path.isdir(full): + continue + try: + yield StrictVersion(n) + except ValueError: + continue diff --git a/migen/build/xilinx/__init__.py b/migen/build/xilinx/__init__.py new file mode 100644 index 00000000..4120abb8 --- /dev/null +++ b/migen/build/xilinx/__init__.py @@ -0,0 +1,2 @@ +from migen.build.xilinx.platform import XilinxPlatform +from migen.build.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept diff --git a/migen/build/xilinx/common.py b/migen/build/xilinx/common.py new file mode 100644 index 00000000..7c753ab6 --- /dev/null +++ b/migen/build/xilinx/common.py @@ -0,0 +1,148 @@ +import os +import sys +from distutils.version import StrictVersion + +from migen.fhdl.std import * +from migen.fhdl.specials import SynthesisDirective +from migen.genlib.cdc import * +from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.genlib.io import * + +from migen.build import tools + + +def settings(path, ver=None, sub=None): + vers = list(tools.versions(path)) + if ver is None: + ver = max(vers) + else: + ver = StrictVersion(ver) + assert ver in vers + + full = os.path.join(path, str(ver)) + if sub: + full = os.path.join(full, sub) + + search = [64, 32] + if tools.arch_bits() == 32: + search.reverse() + + if sys.platform == "win32" or sys.platform == "cygwin": + script_ext = "bat" + else: + script_ext = "sh" + + for b in search: + settings = os.path.join(full, "settings{0}.{1}".format(b, script_ext)) + if os.path.exists(settings): + return settings + + raise OSError("no settings file found") + + +class XilinxNoRetimingImpl(Module): + def __init__(self, reg): + self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg) + + +class XilinxNoRetiming: + @staticmethod + def lower(dr): + return XilinxNoRetimingImpl(dr.reg) + + +class XilinxMultiRegImpl(MultiRegImpl): + def __init__(self, *args, **kwargs): + MultiRegImpl.__init__(self, *args, **kwargs) + self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r) + for r in self.regs] + + +class XilinxMultiReg: + @staticmethod + def lower(dr): + return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n) + + +class XilinxAsyncResetSynchronizerImpl(Module): + def __init__(self, cd, async_reset): + rst1 = Signal() + self.specials += [ + Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset, + i_CE=1, i_C=cd.clk, o_Q=rst1), + Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset, + i_CE=1, i_C=cd.clk, o_Q=cd.rst) + ] + + +class XilinxAsyncResetSynchronizer: + @staticmethod + def lower(dr): + return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) + + +class XilinxDifferentialInputImpl(Module): + def __init__(self, i_p, i_n, o): + self.specials += Instance("IBUFDS", i_I=i_p, i_IB=i_n, o_O=o) + + +class XilinxDifferentialInput: + @staticmethod + def lower(dr): + return XilinxDifferentialInputImpl(dr.i_p, dr.i_n, dr.o) + + +class XilinxDifferentialOutputImpl(Module): + def __init__(self, i, o_p, o_n): + self.specials += Instance("OBUFDS", i_I=i, o_O=o_p, o_OB=o_n) + + +class XilinxDifferentialOutput: + @staticmethod + def lower(dr): + return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) + + +class XilinxDDROutputImpl(Module): + def __init__(self, i1, i2, o, clk): + self.specials += Instance("ODDR2", + p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC", + i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0, + i_D0=i1, i_D1=i2, o_Q=o, + ) + + +class XilinxDDROutput: + @staticmethod + def lower(dr): + return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) + + +xilinx_special_overrides = { + NoRetiming: XilinxNoRetiming, + MultiReg: XilinxMultiReg, + AsyncResetSynchronizer: XilinxAsyncResetSynchronizer, + DifferentialInput: XilinxDifferentialInput, + DifferentialOutput: XilinxDifferentialOutput, + DDROutput: XilinxDDROutput +} + + +class XilinxDDROutputImplS7(Module): + def __init__(self, i1, i2, o, clk): + self.specials += Instance("ODDR", + p_DDR_CLK_EDGE="SAME_EDGE", + i_C=clk, i_CE=1, i_S=0, i_R=0, + i_D1=i1, i_D2=i2, o_Q=o, + ) + + +class XilinxDDROutputS7: + @staticmethod + def lower(dr): + return XilinxDDROutputImplS7(dr.i1, dr.i2, dr.o, dr.clk) + + +xilinx_s7_special_overrides = { + DDROutput: XilinxDDROutputS7 +} diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py new file mode 100644 index 00000000..19896038 --- /dev/null +++ b/migen/build/xilinx/ise.py @@ -0,0 +1,205 @@ +import os +import subprocess +import sys + +from migen.fhdl.std import * +from migen.fhdl.structure import _Fragment + +from migen.build.generic_platform import * +from migen.build import tools +from migen.build.xilinx import common + + +def _format_constraint(c): + if isinstance(c, Pins): + return "LOC=" + c.identifiers[0] + elif isinstance(c, IOStandard): + return "IOSTANDARD=" + c.name + elif isinstance(c, Drive): + return "DRIVE=" + str(c.strength) + elif isinstance(c, Misc): + return c.misc + + +def _format_ucf(signame, pin, others, resname): + fmt_c = [] + for c in [Pins(pin)] + others: + fc = _format_constraint(c) + if fc is not None: + fmt_c.append(fc) + fmt_r = resname[0] + ":" + str(resname[1]) + if resname[2] is not None: + fmt_r += "." + resname[2] + return "NET \"" + signame + "\" " + " | ".join(fmt_c) + "; # " + fmt_r + "\n" + + +def _build_ucf(named_sc, named_pc): + r = "" + for sig, pins, others, resname in named_sc: + if len(pins) > 1: + for i, p in enumerate(pins): + r += _format_ucf(sig + "(" + str(i) + ")", p, others, resname) + else: + r += _format_ucf(sig, pins[0], others, resname) + if named_pc: + r += "\n" + "\n\n".join(named_pc) + return r + + +def _build_xst_files(device, sources, vincpaths, build_name, xst_opt): + prj_contents = "" + for filename, language, library in sources: + prj_contents += language + " " + library + " " + filename + "\n" + tools.write_to_file(build_name + ".prj", prj_contents) + + xst_contents = """run +-ifn {build_name}.prj +-top top +{xst_opt} +-ofn {build_name}.ngc +-p {device} +""".format(build_name=build_name, xst_opt=xst_opt, device=device) + for path in vincpaths: + xst_contents += "-vlgincdir " + path + "\n" + tools.write_to_file(build_name + ".xst", xst_contents) + + +def _run_yosys(device, sources, vincpaths, build_name): + ys_contents = "" + incflags = "" + for path in vincpaths: + incflags += " -I" + path + for filename, language, library in sources: + ys_contents += "read_{}{} {}\n".format(language, incflags, filename) + + ys_contents += """hierarchy -check -top top +proc; memory; opt; fsm; opt +synth_xilinx -top top -edif {build_name}.edif""".format(build_name=build_name) + + ys_name = build_name + ".ys" + tools.write_to_file(ys_name, ys_contents) + r = subprocess.call(["yosys", ys_name]) + if r != 0: + raise OSError("Subprocess failed") + + +def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt, + bitgen_opt, ise_commands, map_opt, par_opt, ver=None): + if sys.platform == "win32" or sys.platform == "cygwin": + source_cmd = "call " + script_ext = ".bat" + shell = ["cmd", "/c"] + build_script_contents = "@echo off\nrem Autogenerated by Migen\n" + else: + source_cmd = "source " + script_ext = ".sh" + shell = ["bash"] + build_script_contents = "# Autogenerated by Migen\nset -e\n" + if source: + settings = common.settings(ise_path, ver, "ISE_DS") + build_script_contents += source_cmd + settings + "\n" + if mode == "edif": + ext = "edif" + else: + ext = "ngc" + build_script_contents += """ +xst -ifn {build_name}.xst +""" + + build_script_contents += """ +ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd +map {map_opt} -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf +par {par_opt} {build_name}_map.ncd {build_name}.ncd {build_name}.pcf +bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit +""" + build_script_contents = build_script_contents.format(build_name=build_name, + ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext, + par_opt=par_opt, map_opt=map_opt) + build_script_contents += ise_commands.format(build_name=build_name) + build_script_file = "build_" + build_name + script_ext + tools.write_to_file(build_script_file, build_script_contents, force_unix=False) + command = shell + [build_script_file] + r = subprocess.call(command) + if r != 0: + raise OSError("Subprocess failed") + + +def _default_ise_path(): + if sys.platform == "win32": + return "C:\\Xilinx" + elif sys.platform == "cygwin": + return "/cygdrive/c/Xilinx" + else: + return "/opt/Xilinx" + + +def _default_source(): + return False if sys.platform == "win32" else True + + +class XilinxISEToolchain: + def __init__(self): + self.xst_opt = """-ifmt MIXED +-use_new_parser yes +-opt_mode SPEED +-register_balancing yes""" + self.map_opt = "-ol high -w" + self.par_opt = "-ol high -w" + self.ngdbuild_opt = "" + self.bitgen_opt = "-g Binary:Yes -w" + self.ise_commands = "" + + def build(self, platform, fragment, build_dir="build", build_name="top", + ise_path=_default_ise_path(), source=_default_source(), run=True, mode="xst"): + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + platform.finalize(fragment) + + ngdbuild_opt = self.ngdbuild_opt + + vns = None + + tools.mkdir_noerror(build_dir) + cwd = os.getcwd() + os.chdir(build_dir) + try: + if mode == "xst" or mode == "yosys": + v_output = platform.get_verilog(fragment) + vns = v_output.ns + named_sc, named_pc = platform.resolve_signals(vns) + v_file = build_name + ".v" + v_output.write(v_file) + sources = platform.sources | {(v_file, "verilog", "work")} + if mode == "xst": + _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt) + isemode = "xst" + else: + _run_yosys(platform.device, sources, platform.verilog_include_paths, build_name) + isemode = "edif" + ngdbuild_opt += "-p " + platform.device + + if mode == "mist": + from mist import synthesize + synthesize(fragment, platform.constraint_manager.get_io_signals()) + + if mode == "edif" or mode == "mist": + e_output = platform.get_edif(fragment) + vns = e_output.ns + named_sc, named_pc = platform.resolve_signals(vns) + e_file = build_name + ".edif" + e_output.write(e_file) + isemode = "edif" + + tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) + if run: + _run_ise(build_name, ise_path, source, isemode, + ngdbuild_opt, self.bitgen_opt, self.ise_commands, + self.map_opt, self.par_opt) + finally: + os.chdir(cwd) + + return vns + + def add_period_constraint(self, platform, clk, period): + platform.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}"; +TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk) diff --git a/migen/build/xilinx/platform.py b/migen/build/xilinx/platform.py new file mode 100644 index 00000000..c5422282 --- /dev/null +++ b/migen/build/xilinx/platform.py @@ -0,0 +1,33 @@ +from migen.build.generic_platform import GenericPlatform +from migen.build.xilinx import common, vivado, ise + + +class XilinxPlatform(GenericPlatform): + bitstream_ext = ".bit" + + def __init__(self, *args, toolchain="ise", **kwargs): + GenericPlatform.__init__(self, *args, **kwargs) + if toolchain == "ise": + self.toolchain = ise.XilinxISEToolchain() + elif toolchain == "vivado": + self.toolchain = vivado.XilinxVivadoToolchain() + else: + raise ValueError("Unknown toolchain") + + def get_verilog(self, *args, special_overrides=dict(), **kwargs): + so = dict(common.xilinx_special_overrides) + if self.device[:3] == "xc7": + so.update(dict(common.xilinx_s7_special_overrides)) + so.update(special_overrides) + return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) + + def get_edif(self, fragment, **kwargs): + return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs) + + def build(self, *args, **kwargs): + return self.toolchain.build(self, *args, **kwargs) + + def add_period_constraint(self, clk, period): + if hasattr(clk, "p"): + clk = clk.p + self.toolchain.add_period_constraint(self, clk, period) diff --git a/migen/build/xilinx/programmer.py b/migen/build/xilinx/programmer.py new file mode 100644 index 00000000..644c9f7d --- /dev/null +++ b/migen/build/xilinx/programmer.py @@ -0,0 +1,199 @@ +import os +import sys +import subprocess + +from migen.build.generic_programmer import GenericProgrammer +from migen.build.xilinx import common + + +def _run_urjtag(cmds): + with subprocess.Popen("jtag", stdin=subprocess.PIPE) as process: + process.stdin.write(cmds.encode("ASCII")) + process.communicate() + + +class UrJTAG(GenericProgrammer): + needs_bitreverse = True + + def __init__(self, cable, flash_proxy_basename=None): + GenericProgrammer.__init__(self, flash_proxy_basename) + self.cable = cable + + def load_bitstream(self, bitstream_file): + cmds = """cable {cable} +detect +pld load {bitstream} +quit +""".format(bitstream=bitstream_file, cable=self.cable) + _run_urjtag(cmds) + + def flash(self, address, data_file): + flash_proxy = self.find_flash_proxy() + cmds = """cable {cable} +detect +pld load "{flash_proxy}" +initbus fjmem opcode=000010 +frequency 6000000 +detectflash 0 +endian big +flashmem "{address}" "{data_file}" noverify +""".format(flash_proxy=flash_proxy, address=address, data_file=data_file, + cable=self.cable) + _run_urjtag(cmds) + + +class XC3SProg(GenericProgrammer): + needs_bitreverse = False + + def __init__(self, cable, flash_proxy_basename=None): + GenericProgrammer.__init__(self, flash_proxy_basename) + self.cable = cable + + def load_bitstream(self, bitstream_file): + subprocess.call(["xc3sprog", "-v", "-c", self.cable, bitstream_file]) + + def flash(self, address, data_file): + flash_proxy = self.find_flash_proxy() + subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)]) + + + +class FpgaProg(GenericProgrammer): + needs_bitreverse = False + + def __init__(self, flash_proxy_basename=None): + GenericProgrammer.__init__(self, flash_proxy_basename) + + def load_bitstream(self, bitstream_file): + subprocess.call(["fpgaprog", "-v", "-f", bitstream_file]) + + def flash(self, address, data_file): + if address != 0: + raise ValueError("fpga prog needs a main bitstream at address 0") + flash_proxy = self.find_flash_proxy() + subprocess.call(["fpgaprog", "-v", "-sa", "-r", "-b", flash_proxy, + "-f", data_file]) + + +def _run_impact(cmds): + with subprocess.Popen("impact -batch", stdin=subprocess.PIPE, shell=True) as process: + process.stdin.write(cmds.encode("ASCII")) + process.communicate() + return process.returncode + + +def _create_xsvf(bitstream_file, xsvf_file): + assert os.path.exists(bitstream_file), bitstream_file + assert not os.path.exists(xsvf_file), xsvf_file + assert 0 == _run_impact(""" +setPreference -pref KeepSVF:True +setMode -bs +setCable -port xsvf -file {xsvf} +addDevice -p 1 -file {bitstream} +program -p 1 +quit +""".format(bitstream=bitstream_file, xsvf=xsvf_file)) + + +class iMPACT(GenericProgrammer): + needs_bitreverse = False + + def load_bitstream(self, bitstream_file): + cmds = """setMode -bs +setCable -p auto +addDevice -p 1 -file {bitstream} +program -p 1 +quit +""".format(bitstream=bitstream_file) + _run_impact(cmds) + + +def _run_vivado(path, ver, cmds): + if sys.platform == "win32" or sys.platform == "cygwin": + vivado_cmd = "vivado -mode tcl" + else: + settings = common.settings(path, ver) + vivado_cmd = "bash -c \"source " + settings + "&& vivado -mode tcl\"" + with subprocess.Popen(vivado_cmd, stdin=subprocess.PIPE, shell=True) as process: + process.stdin.write(cmds.encode("ASCII")) + process.communicate() + + +class VivadoProgrammer(GenericProgrammer): + needs_bitreverse = False + def __init__(self, vivado_path="/opt/Xilinx/Vivado", vivado_ver=None): + GenericProgrammer.__init__(self) + self.vivado_path = vivado_path + self.vivado_ver = vivado_ver + + def load_bitstream(self, bitstream_file): + cmds = """open_hw +connect_hw_server +open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] + +set_property PROBES.FILE {{}} [lindex [get_hw_devices] 0] +set_property PROGRAM.FILE {{{bitstream}}} [lindex [get_hw_devices] 0] + +program_hw_devices [lindex [get_hw_devices] 0] +refresh_hw_device [lindex [get_hw_devices] 0] + +quit +""".format(bitstream=bitstream_file) + _run_vivado(self.vivado_path, self.vivado_ver, cmds) + + # XXX works to flash bitstream, adapt it to flash bios + def flash(self, address, data_file): + cmds = """open_hw +connect_hw_server +open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] +create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {{n25q256-3.3v-spi-x1_x2_x4}}] 0] + +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +refresh_hw_device [lindex [get_hw_devices] 0] + +set_property PROGRAM.ADDRESS_RANGE {{use_file}} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.FILES [list "{data}" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] +set_property PROGRAM.UNUSED_PIN_TERMINATION {{pull-none}} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] + +startgroup +if {{![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] }} {{ create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; }}; +program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] +endgroup + +quit +""".format(data=data_file) + _run_vivado(self.vivado_path, self.vivado_ver, cmds) + + +class Adept(GenericProgrammer): + """Using the Adept tool with an onboard Digilent "USB JTAG" cable. + + You need to install Adept Utilities V2 from + http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2 + """ + + needs_bitreverse = False + + def __init__(self, board, index, flash_proxy_basename=None): + GenericProgrammer.__init__(self, flash_proxy_basename) + self.board = board + self.index = index + + def load_bitstream(self, bitstream_file): + subprocess.call([ + "djtgcfg", + "--verbose", + "prog", "-d", self.board, + "-i", str(self.index), + "-f", bitstream_file, + ]) + + def flash(self, address, data_file): + raise ValueError("Flashing unsupported with DigilentAdept tools") diff --git a/migen/build/xilinx/vivado.py b/migen/build/xilinx/vivado.py new file mode 100644 index 00000000..8d85885f --- /dev/null +++ b/migen/build/xilinx/vivado.py @@ -0,0 +1,138 @@ +# This file is Copyright (c) 2014 Florent Kermarrec +# License: BSD + +import os +import subprocess +import sys + +from migen.fhdl.std import * +from migen.fhdl.structure import _Fragment + +from migen.build.generic_platform import * +from migen.build import tools +from migen.build.xilinx import common + + +def _format_constraint(c): + if isinstance(c, Pins): + return "set_property LOC " + c.identifiers[0] + elif isinstance(c, IOStandard): + return "set_property IOSTANDARD " + c.name + elif isinstance(c, Drive): + return "set_property DRIVE " + str(c.strength) + elif isinstance(c, Misc): + return "set_property " + c.misc.replace("=", " ") + else: + raise ValueError("unknown constraint {}".format(c)) + + +def _format_xdc(signame, resname, *constraints): + fmt_c = [_format_constraint(c) for c in constraints] + fmt_r = resname[0] + ":" + str(resname[1]) + if resname[2] is not None: + fmt_r += "." + resname[2] + r = " ## {}\n".format(fmt_r) + for c in fmt_c: + r += c + " [get_ports " + signame + "]\n" + return r + + +def _build_xdc(named_sc, named_pc): + r = "" + for sig, pins, others, resname in named_sc: + if len(pins) > 1: + for i, p in enumerate(pins): + r += _format_xdc(sig + "[" + str(i) + "]", resname, Pins(p), *others) + elif pins: + r += _format_xdc(sig, resname, Pins(pins[0]), *others) + else: + r += _format_xdc(sig, resname, *others) + if named_pc: + r += "\n" + "\n\n".join(named_pc) + return r + + +def _run_vivado(build_name, vivado_path, source, ver=None): + if sys.platform == "win32" or sys.platform == "cygwin": + build_script_contents = "REM Autogenerated by Migen\n" + build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n" + build_script_file = "build_" + build_name + ".bat" + tools.write_to_file(build_script_file, build_script_contents) + r = subprocess.call([build_script_file]) + else: + build_script_contents = "# Autogenerated by Migen\nset -e\n" + settings = common.settings(vivado_path, ver) + build_script_contents += "source " + settings + "\n" + build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n" + build_script_file = "build_" + build_name + ".sh" + tools.write_to_file(build_script_file, build_script_contents) + r = subprocess.call(["bash", build_script_file]) + + if r != 0: + raise OSError("Subprocess failed") + + +class XilinxVivadoToolchain: + def __init__(self): + self.bitstream_commands = [] + self.additional_commands = [] + self.pre_synthesis_commands = [] + self.with_phys_opt = False + + def _build_batch(self, platform, sources, build_name): + tcl = [] + for filename, language, library in sources: + tcl.append("add_files " + filename) + tcl.append("set_property library {} [get_files {}]".format(library, filename)) + + tcl.append("read_xdc {}.xdc".format(build_name)) + tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) + tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths))) + tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name)) + tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name)) + tcl.append("place_design") + if self.with_phys_opt: + tcl.append("phys_opt_design -directive AddRetime") + tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name)) + tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name)) + tcl.append("report_io -file {}_io.rpt".format(build_name)) + tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name)) + tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name)) + tcl.append("route_design") + tcl.append("report_route_status -file {}_route_status.rpt".format(build_name)) + tcl.append("report_drc -file {}_drc.rpt".format(build_name)) + tcl.append("report_timing_summary -max_paths 10 -file {}_timing.rpt".format(build_name)) + tcl.append("report_power -file {}_power.rpt".format(build_name)) + for bitstream_command in self.bitstream_commands: + tcl.append(bitstream_command.format(build_name=build_name)) + tcl.append("write_bitstream -force {}.bit ".format(build_name)) + for additional_command in self.additional_commands: + tcl.append(additional_command.format(build_name=build_name)) + tcl.append("quit") + tools.write_to_file(build_name + ".tcl", "\n".join(tcl)) + + def build(self, platform, fragment, build_dir="build", build_name="top", + vivado_path="/opt/Xilinx/Vivado", source=True, run=True): + tools.mkdir_noerror(build_dir) + os.chdir(build_dir) + + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + platform.finalize(fragment) + v_output = platform.get_verilog(fragment) + named_sc, named_pc = platform.resolve_signals(v_output.ns) + v_file = build_name + ".v" + v_output.write(v_file) + sources = platform.sources | {(v_file, "verilog", "work")} + self._build_batch(platform, sources, build_name) + tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc)) + if run: + _run_vivado(build_name, vivado_path, source) + + os.chdir("..") + + return v_output.ns + + def add_period_constraint(self, platform, clk, period): + platform.add_platform_command("""create_clock -name {clk} -period """ + \ + str(period) + """ [get_ports {clk}]""", clk=clk)