From: Sandipan Das <sandipan@linux.ibm.com>
Date: Sat, 6 Feb 2021 11:47:16 +0000 (+0530)
Subject: arch-power: Add doubleword load-store instructions
X-Git-Tag: develop-gem5-snapshot~56
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86f3e9dfba81036ec6bcf4fd18ea293378aeeaee;p=gem5.git

arch-power: Add doubleword load-store instructions

This introduces new formats for DS form instructions and
adds the following instructions.
  * Load Doubleword (ld)
  * Load Doubleword Indexed (ldx)
  * Load Doubleword with Update (ldu)
  * Load Doubleword with Update Indexed (ldux)
  * Store Doubleword (std)
  * Store Doubleword Indexed (stdx)
  * Store Doubleword with Update (stdu)
  * Store Doubleword with Update Indexed (stdux)

Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
---

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e2b392961..67eebcde4 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -134,6 +134,21 @@ decode PO default Unknown::unknown() {
     58: decode DS_XO {
         format LoadDispShiftOp {
             2: lwa({{ Rt = Mem_sw; }});
+            0: ld({{ Rt = Mem; }});
+        }
+
+        format LoadDispShiftUpdateOp {
+            1: ldu({{ Rt = Mem; }});
+        }
+    }
+
+    62: decode DS_XO {
+        format StoreDispShiftOp {
+            0: std({{ Mem = Rs; }});
+        }
+
+        format StoreDispShiftUpdateOp {
+            1: stdu({{ Mem = Rs; }});
         }
     }
 
@@ -236,6 +251,7 @@ decode PO default Unknown::unknown() {
             23: lwzx({{ Rt = Mem_uw; }});
             341: lwax({{ Rt = Mem_sw; }});
             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
+            21: ldx({{ Rt = Mem; }});
             535: lfsx({{ Ft_sf = Mem_sf; }});
             599: lfdx({{ Ft = Mem_df; }});
             855: lfiwax({{ Ft_uw = Mem; }});
@@ -247,6 +263,7 @@ decode PO default Unknown::unknown() {
             375: lhaux({{ Rt = Mem_sh; }});
             55: lwzux({{ Rt = Mem_uw; }});
             373: lwaux({{ Rt = Mem_sw; }});
+            53: ldux({{ Rt = Mem; }});
             567: lfsux({{ Ft_sf = Mem_sf; }});
             631: lfdux({{ Ft = Mem_df; }});
         }
@@ -271,12 +288,14 @@ decode PO default Unknown::unknown() {
                 CR = cr;
                 Rsv = 0;
             }});
+            149: stdx({{ Mem = Rs }});
         }
 
         format StoreIndexUpdateOp {
             247: stbux({{ Mem_ub = Rs_ub; }});
             439: sthux({{ Mem_uh = Rs_uh; }});
             183: stwux({{ Mem_uw = Rs_uw; }});
+            181: stdux({{ Mem = Rs; }});
         }
 
         format IntOp {
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 1dd985406..1cddc409a 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -311,6 +311,16 @@ def format LoadDispShiftOp(memacc_code,
 }};
 
 
+def format StoreDispShiftOp(memacc_code,
+                            ea_code = {{ EA = Ra + (disp << 2); }},
+                            ea_code_ra0 = {{ EA = (disp << 2); }},
+                            mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+                 'MemDispShiftOp', 'Store', mem_flags, inst_flags)
+}};
+
+
 def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                             mem_flags = [], inst_flags = []) {{
 
@@ -339,3 +349,35 @@ def format StoreDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                       decode_template = CheckRaZeroDecode,
                       exec_template_base = 'Store')
 }};
+
+
+def format LoadDispShiftUpdateOp(memacc_code,
+                                 ea_code = {{ EA = Ra + (disp << 2); }},
+                                 mem_flags = [], inst_flags = []) {{
+
+    # Add in the update code
+    memacc_code += 'Ra = EA;'
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      base_class = 'MemDispShiftOp',
+                      decode_template = CheckRaRtDecode,
+                      exec_template_base = 'Load')
+}};
+
+
+def format StoreDispShiftUpdateOp(memacc_code,
+                                  ea_code = {{ EA = Ra + (disp << 2); }},
+                                  mem_flags = [], inst_flags = []) {{
+
+    # Add in the update code
+    memacc_code += 'Ra = EA;'
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      base_class = 'MemDispShiftOp',
+                      decode_template = CheckRaZeroDecode,
+                      exec_template_base = 'Store')
+}};