From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 Sep 2021 13:21:23 +0000 (+0100)
Subject: create new function teststate_check_regs which is called by check_regs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=86f52a45b43bfc596ebf7217cbb1cc2ce0354204;p=soc.git

create new function teststate_check_regs which is called by check_regs
teststate_checkregs does not care how many pieces of state it is asked
to compare. could be 2, could be 3, could be 30
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 608c442c..0be2a292 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -149,12 +149,23 @@ def setup_regs(pdecode2, core, test):
     print("oe:", oe, oe_ok)
 
 
+def teststate_check_regs(dut, states, test, code):
+    """teststate_check_regs: compares a set of Power ISA objects
+    to check if they have the same "state" (registers only, at the moment)
+    """
+    slist = []
+    for stype, totest in states.items():
+        state = yield from TestState(stype, totest, dut, code)
+        slist.append(state)
+    for i in range(len(slist)-1):
+        state, against = slist[i], slist[i+1]
+        state.compare(against)
+
+
 def check_regs(dut, sim, core, test, code):
     # create the two states and compare
     testdic = {'sim': sim, 'hdl': core}
-    simstate = yield from TestState('sim', testdic, dut, code)
-    corestate = yield from TestState('hdl', testdic, dut, code)
-    simstate.compare(corestate)
+    yield from teststate_check_regs(dut, testdic, test, code)
 
 
 def wait_for_busy_hi(cu):
diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index 9b45f506..f10d2462 100644
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -124,10 +124,14 @@ class HDLState(State):
         print("class hdl pc", hex(self.pc))
 
 
-def TestState(state_type, state_dic, dut, code):
-    state_factory = {'sim': SimState, 'hdl': HDLState}
+global state_factory
+state_factory = {'sim': SimState, 'hdl': HDLState}
+
+
+def TestState(state_type, to_test, dut, code):
     state_class = state_factory[state_type]
-    state = state_class(state_dic[state_type])
+    state = state_class(to_test)
+    state.to_test = to_test
     state.dut = dut
     state.state_type = state_type
     state.code = code