From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Sep 2021 12:49:52 +0000 (+0100)
Subject: code-comments and dummy functions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87042ef15585c7b0482dede64a2ad1418c1e3441;p=soc.git

code-comments and dummy functions
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index b16a68f3..31c6b7b4 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -325,6 +325,8 @@ class TestRunner(FHDLTestCase):
         intclk = ClockSignal("coresync")
         comb += intclk.eq(ClockSignal())
 
+        # TODO these should probably move into HDLRunner's constructor
+        # and become HDLRunner.pc_i and HDLRunner.svstate_i
         if self.run_hdl:
 
             pc_i = Signal(32)
@@ -343,6 +345,9 @@ class TestRunner(FHDLTestCase):
             ###### PREPARATION PHASE AT START OF RUNNING #######
             # StateRunner.setup_during_test()
 
+            if self.run_sim:
+                simrun.setup_during_test() # TODO, some arguments?
+
             if self.run_hdl:
                 # start in stopped
                 yield from set_dmi(hdlrun.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)