From: Florent Kermarrec Date: Mon, 17 Jun 2019 07:55:27 +0000 (+0200) Subject: integration/soc_core: move cpu_variant checks/formating to cpu X-Git-Tag: 24jan2021_ls180~1160 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87118d509c3f0a0bdd96137a0a5bb4149e5cc46a;p=litex.git integration/soc_core: move cpu_variant checks/formating to cpu --- diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index 5b4877c3..891e846a 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -4,3 +4,66 @@ from litex.soc.cores.cpu.picorv32 import PicoRV32 from litex.soc.cores.cpu.vexriscv import VexRiscv from litex.soc.cores.cpu.minerva import Minerva from litex.soc.cores.cpu.rocket import RocketRV64 + +# CPU Variants/Extensions Definition --------------------------------------------------------------- + +CPU_VARIANTS = { + # "official name": ["alias 1", "alias 2"], + "minimal" : ["min",], + "lite" : ["light", "zephyr", "nuttx"], + "standard": [None, "std"], + "full": [], + "linux" : [], +} +CPU_VARIANTS_EXTENSIONS = ["debug", "no-dsp"] + + +class InvalidCPUVariantError(ValueError): + def __init__(self, variant): + msg = """\ +Invalid cpu_variant value: {} + +Possible Values: +""".format(variant) + for k, v in CPU_VARIANTS.items(): + msg += " - {} (aliases: {})\n".format(k, ", ".join(str(s) for s in v)) + ValueError.__init__(self, msg) + + +class InvalidCPUExtensionError(ValueError): + def __init__(self, variant): + msg = """\ +Invalid extension in cpu_variant value: {} + +Possible Values: +""".format(variant) + for e in CPU_VARIANTS_EXTENSIONS: + msg += " - {}\n".format(e) + ValueError.__init__(self, msg) + +# CPU Variants/Extensions Check/Format ------------------------------------------------------------- + + +def check_format_cpu_variant(variant): + # Support the old style which used underscore for separator + if variant is None: + variant = "standard" + variant = variant.replace('_', '+') + + # Check for valid CPU variants. + processor, *extensions = variant.split('+') + for k, v in CPU_VARIANTS.items(): + if processor not in [k,]+v: + continue + _variant = k + break + else: + raise InvalidCPUVariantError(variant) + + # Check for valid CPU extensions. + for extension in sorted(extensions): + if extension not in CPU_VARIANTS_EXTENSIONS: + raise InvalidCPUExtensionError(variant) + _variant += "+"+extension + + return _variant diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 4e03b531..0db88e0b 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -13,7 +13,7 @@ from migen import * from litex.build.tools import deprecated_warning from litex.soc.cores import identifier, timer, uart -from litex.soc.cores.cpu import * +from litex.soc.cores import cpu from litex.soc.interconnect.csr import * from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr @@ -27,42 +27,6 @@ __all__ = [ "soc_core_argdict" ] -# CPU Variants ------------------------------------------------------------------------------------- - -CPU_VARIANTS = { - # "official name": ["alias 1", "alias 2"], - "minimal" : ["min",], - "lite" : ["light", "zephyr", "nuttx"], - "standard": [None, "std"], - "full": [], - "linux" : [], -} -CPU_VARIANTS_EXTENSIONS = ["debug"] - - -class InvalidCPUVariantError(ValueError): - def __init__(self, variant): - msg = """\ -Invalid cpu_variant value: {} - -Possible Values: -""".format(variant) - for k, v in CPU_VARIANTS.items(): - msg += " - {} (aliases: {})\n".format(k, ", ".join(str(s) for s in v)) - ValueError.__init__(self, msg) - - -class InvalidCPUExtensionError(ValueError): - def __init__(self, variant): - msg = """\ -Invalid extension in cpu_variant value: {} - -Possible Values: -""".format(variant) - for e in CPU_VARIANTS_EXTENSIONS: - msg += " - {}\n".format(e) - ValueError.__init__(self, msg) - # Helpers ------------------------------------------------------------------------------------------ def version(with_time=True): @@ -218,26 +182,7 @@ class SoCCore(Module): cpu_type = None self.cpu_type = cpu_type - # Support the old style which used underscore for separator - if cpu_variant is None: - cpu_variant = "standard" - cpu_variant = cpu_variant.replace('_', '+') - - # Check for valid CPU variants. - cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+') - for key, values in CPU_VARIANTS.items(): - if cpu_variant_processor not in [key,]+values: - continue - self.cpu_variant = key - break - else: - raise InvalidCPUVariantError(cpu_variant) - - # Check for valid CPU extensions. - for ext in sorted(cpu_variant_ext): - if ext not in CPU_VARIANTS_EXTENSIONS: - raise InvalidCPUExtensionError(cpu_variant) - self.cpu_variant += "+"+ext + self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant) if integrated_rom_size: cpu_reset_address = self.soc_mem_map["rom"] @@ -277,19 +222,19 @@ class SoCCore(Module): if cpu_type is not None: # CPU selection / instance if cpu_type == "lm32": - self.add_cpu(lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant)) + self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "mor1kx" or cpu_type == "or1k": if cpu_type == "or1k": deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"") - self.add_cpu(mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant)) + self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "picorv32": - self.add_cpu(picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) + self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "vexriscv": - self.add_cpu(vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant)) + self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "minerva": - self.add_cpu(minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant)) + self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "rocket": - self.add_cpu(rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant)) + self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type))