From: Yehowshua <Yehowshua@web>
Date: Tue, 5 May 2020 15:51:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2722
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87251d857d6dca8d141f302adff3afb05b1a3185;p=libreriscv.git

---

diff --git a/Documentation/SOC/index.mdwn b/Documentation/SOC/index.mdwn
index 726b459ec..4d4096349 100644
--- a/Documentation/SOC/index.mdwn
+++ b/Documentation/SOC/index.mdwn
@@ -12,6 +12,7 @@ Below is the POWER add insruction.
 | 0b0100001010 | ALU  | OP_ADD      | RA  | RB  | NONE | RT  | 0     | 0      | 0     | 0       | ZERO   | 0       | NONE     | 0  | 0       | 0   | 0    | 0   | 0   | RC | 0  | 0        | add     | XO   |
 
 Here is an example of a toy multiplexer that sets various fields in the PowerOP signal class to the correct values for the add instruction when select==1 is set.
+This should give you a feel for how we work with enums and PowerOP.
 
     from nmigen import Module, Elaboratable, Signal, Cat, Mux
     from soc.decoder.power_enums import (Function, Form, InternalOp,