From: Richard Earnshaw Date: Wed, 18 Sep 2002 14:01:58 +0000 (+0000) Subject: re PR rtl-optimization/7967 (optimization produces wrong code (ARM)) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=872e50d35b5f4ec30a769823bd5b6ed84da89b39;p=gcc.git re PR rtl-optimization/7967 (optimization produces wrong code (ARM)) PR optimization/7967 * arm.md (ne_zeroextractsi): Add clobber of the condition code register. From-SVN: r57278 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fcf11dd27d0..ee2543a4414 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2002-09-18 Richard Earnshaw (reanrsha@arm.com) + + PR optimization/7967 + * arm.md (ne_zeroextractsi): Add clobber of the condition code + register. + 2002-09-18 Kazu Hirata * config/s390/s390.c: Follow spelling convention. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b56955d3b80..a830462be20 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1838,7 +1838,8 @@ (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "const_int_operand" "n") (match_operand:SI 3 "const_int_operand" "n")) - (const_int 0)))] + (const_int 0))) + (clobber (reg:CC CC_REGNUM))] "TARGET_ARM && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32 && INTVAL (operands[2]) > 0