From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 10:54:10 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~534
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=872f67681f23dfda4e18ee19340a6c8683c79297;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index a27179676..8cf85ada9 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -91,15 +91,23 @@ which succeeds.  If VLI (Vector Length Inclusive) is clear, VL is truncated
 to *exclude* the current element, otherwise it is included. SVSTATE.MVL is not changed.
 
 svstep mode will run an increment of SVSTATE srcstep and dststep
-(only meaningful in Vertical First Mode).  Unlike `svstep.` however
+(which is still useful in Horizontal First Mode).  Unlike `svstep.` however
 which updates only CR0 with the testing of REMAP loop progress,
 the CR Field is taken from the branch `BI` field, and updated
-prior to proceeding to branch conditional testing.
+prior to proceeding to each element branch conditional testing.
 
 Note that, interestingly, due to the useful side-effects of `VLSET` mode
 and `svstep` mode it is actually useful to use Branch Conditional even
 to perform no actual branch operation, i.e to point to the instruction
 after the branch.
+In particular, svstep mode is still useful for Horizontal-First Mode
+particularly in combination with REMAP. All "loop end" conditions
+will be tested on a per-element basis and placed into a Vector of
+CRs starting from the point specified by the Branch `BI` field.
+This Vector of CR Fields may then be subsequently used as a Predicate
+Mask, and, furthermore, if VLSET mode was requested, VL will have
+been set to the length of one of the loop endpoints, again as specified
+by the bit from the Branch `BI` field.
 
 Available options to combine:
 
@@ -119,9 +127,14 @@ Pseudocode for Horizontal-First Mode:
    else
        cond_ok = not SVRMmode.ALL
        for srcstep in range(VL):
+           new_srcstep, CRbits = SVSTATE_NEXT(srcstep)
            # select predicate bit or zero/one
            if predicate[srcstep]:
-               testbit = CR[BI+32+srcstep*4]
+               # get SVP64 extended CR field 0..127
+               SVCRf = SVP64EXTRA(BI>>2)
+               CR{SVCRf+srcstep} = CRbits
+               testbit = CRbits[BI & 0b11]
+               # testbit = CR[BI+32+srcstep*4]
            else if not SVRMmode.sz:
                continue
            else
@@ -169,7 +182,6 @@ Pseudocode for Vertical-First Mode:
            testbit = SVRMmode.SNZ
        # actual element test here
        cond_ok <- ¬(testbit ^ BO[1])
-
        # test for VL to be set (and exit)
        if ~cond_ok and VLSET
            if SVRMmode.VLI