From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Wed, 17 Mar 2021 17:30:49 +0000 (+0100)
Subject: ast: Use better parameter serialization for paramod names.
X-Git-Tag: yosys-0.10~244
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8740fdf1d799fd8a3196bac28fe4e418e74f2acc;p=yosys.git

ast: Use better parameter serialization for paramod names.

Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
---

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 7aa391c93..84a4de41c 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1575,6 +1575,29 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 	return modname;
 }
 
+static std::string serialize_param_value(const RTLIL::Const &val) {
+	std::string res;
+	if (val.flags & RTLIL::ConstFlags::CONST_FLAG_STRING)
+		res.push_back('t');
+	if (val.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED)
+		res.push_back('s');
+	if (val.flags & RTLIL::ConstFlags::CONST_FLAG_REAL)
+		res.push_back('r');
+	res += stringf("%d", GetSize(val));
+	res.push_back('\'');
+	for (int i = GetSize(val) - 1; i >= 0; i--) {
+		switch (val.bits[i]) {
+			case RTLIL::State::S0: res.push_back('0'); break;
+			case RTLIL::State::S1: res.push_back('1'); break;
+			case RTLIL::State::Sx: res.push_back('x'); break;
+			case RTLIL::State::Sz: res.push_back('z'); break;
+			case RTLIL::State::Sa: res.push_back('?'); break;
+			case RTLIL::State::Sm: res.push_back('m'); break;
+		}
+	}
+	return res;
+}
+
 // create a new parametric module (when needed) and return the name of the generated module
 std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet)
 {
@@ -1594,14 +1617,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
 		if (it != parameters.end()) {
 			if (!quiet)
 				log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
-			para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second));
+			para_info += stringf("%s=%s", child->str.c_str(), serialize_param_value(it->second).c_str());
 			continue;
 		}
 		it = parameters.find(stringf("$%d", para_counter));
 		if (it != parameters.end()) {
 			if (!quiet)
 				log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
-			para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second));
+			para_info += stringf("%s=%s", child->str.c_str(), serialize_param_value(it->second).c_str());
 			continue;
 		}
 	}
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index 210e87477..0ba3901f7 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
 FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
 endmodule
 EOT
-logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 8 t:FD*