From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 3 Aug 2020 15:51:13 +0000 (+0200)
Subject: Fix sel test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87432e10463bae8205ac922eec405a5e40de5429;p=gram.git

Fix sel test
---

diff --git a/gram/test/test_frontend_wishbone.py b/gram/test/test_frontend_wishbone.py
index 02a9290..865e74a 100644
--- a/gram/test/test_frontend_wishbone.py
+++ b/gram/test/test_frontend_wishbone.py
@@ -236,9 +236,9 @@ class GramWishboneTestCase(FHDLTestCase):
 
             self.assertEqual((yield native_port.wdata.we), 1)
 
-            yield bus.stb.eq(0)
-            yield bus.cyc.eq(0)
-            yield native_port.wdata.ready.eq(0)
+            yield dut.bus.stb.eq(0)
+            yield dut.bus.cyc.eq(0)
+            yield dut.native_port.wdata.ready.eq(0)
             yield
 
         runSimulation(dut, process, "test_frontend_wishbone.vcd")