From: Renlin Li <renlin.li@arm.com>
Date: Thu, 12 Nov 2015 10:14:35 +0000 (+0000)
Subject: [PATCH][ARM]Fix addsi3_compare_op2 pattern.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87494f556989cda8c12041d0a6e242ca99b3c957;p=gcc.git

[PATCH][ARM]Fix addsi3_compare_op2 pattern.

gcc/

2015-11-12  Renlin Li  <renlin.li@arm.com>

	* config/arm/arm.md (addsi3_compare_op2): Make the order of
	assembly pattern consistent with constraint order.

From-SVN: r230222
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0b68dfaecbc..db14b226ce8 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-11-12  Renlin Li  <renlin.li@arm.com>
+
+	* config/arm/arm.md (addsi3_compare_op2): Make the order of
+	assembly pattern consistent with constraint order.
+
 2015-11-12  Tom de Vries  <tom@codesourcery.com>
 
 	* gen-pass-instances.awk (handle_line): Simplify match regexp.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 8ebb1bfd221..73c308825c4 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -747,8 +747,8 @@
   "TARGET_32BIT"
   "@
    adds%?\\t%0, %1, %2
-   adds%?\\t%0, %1, %2
-   subs%?\\t%0, %1, #%n2"
+   subs%?\\t%0, %1, #%n2
+   adds%?\\t%0, %1, %2"
   [(set_attr "conds" "set")
    (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
 )