From: lkcl <lkcl@web>
Date: Thu, 7 Apr 2022 16:25:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2860
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=875506dcd21524c066b8a31cd13997d7c54c6759;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index ceb5022cc..810ef644f 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -193,11 +193,12 @@ Brief description of fields:
   VL is truncated to *exclude* the current element, otherwise it is
   included. SVSTATE.MVL is not altered: only VL.
 * **LRu**: Link Register Update, used in conjunction with LK=1.
-  When LRu=1,LK=0, Link Register is updated unconditionally.
-  When LRu=1,LK=1, Link Register will
+  - When LRu=0,LK=1, Link Register is updated unconditionally.
+  - When LRu=1,LK=1, Link Register will
   only be updated if the Branch Condition succeeds.
-  When LRu=0,LK=1, Link Register will only be updated if
-  the Branch Condition fails. This avoids
+  - When LRu=1,LK=0, Link Register will only be updated if
+  the Branch Condition fails.
+  - This avoids
   destruction of LR during loops (particularly Vertical-First
   ones).
 * **VSb** In VLSET Mode, after testing,