From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 06:36:00 +0000 (+0100)
Subject: alter STATE CSR to support subvl
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8760590bbd18ccab3c259754b0ab9d3c8751a98f;p=riscv-isa-sim.git

alter STATE CSR to support subvl
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 09467bc..c6d604a 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -890,7 +890,8 @@ reg_t processor_t::get_csr(int which)
     case CSR_USVSTATE:
       return (state.sv().vl-1)            | ((state.sv().mvl-1)<<6) |
              (state.sv().srcoffs<<12)     | (state.sv().destoffs<<18) |
-             (state.sv().state_bank<<24)  | (state.sv().state_size<<26);
+             ((state.sv().subvl-1)<<24)   |
+             (state.sv().ssvoffs<<26)     | (state.sv().dsvoffs<<28);
     case CSR_USVMVL:
       return state.sv().mvl;
     case CSR_SVREGTOP: